Around-the-clock watch for ERA

Inscriptions: Verso: [stamped] Photograph by Freda Leinwand. [463 West Street, Studio 229G, New York, NY 10014].

Around-the-clock watch for ERA

Inscriptions: Verso: [stamped] Photograph by Freda Leinwand. [463 West Street, Studio 229G, New York, NY 10014].

All-analogue real-time filter bank OFDM over 50 Km of SSMF using a novel synchronization technique

A 21.6 Gbit/s 1.78 bit/s/Hz OFDM signal is transmitted over 50 Km of fiber without using DSP in the transmitter or the receiver. The synchronization scheme only requires one PLL to synchronize all the subcarriers.

Collective excitability, synchronization, and array-enhanced coherence resonance in a population of lasers with a saturable absorber

In this article we present a numerical study of the collective dynamics in a population of coupled semiconductor lasers with a saturable absorber, operating in the excitable regime under the action of additive noise. We demonstrate that temporal and intensity synchronization takes place in a broad region of the parameter space and for various array sizes. The synchronization is robust and occurs even for a set of nonidentical coupled lasers. The cooperative nature of the system results in a self-organization process which enhances the coherence of the single element of the population too and can have broad impact for detection purposes, for building all-optical simulators of neural networks and in the field of photonics-based computation.

Time beyond clock: time use-surveys revisited

Time use surveys -despite having represented a turning point in the study of inequalities between women and men- continue hiding care times and subtracting relevance to the qualitative dimensions of time. This due both, to the ideological conception that lies behind this type of studies that consider more relevant market process as to surveys methodology. This article analyzes the theoretical model that lies behind time use surveys and, consequently, the study of the conceptual aspects, the methodology and the potential of these surveys as an analytical instrument. The aim is to unraveling the limitations presented by the surveys to take in account the subjective dimensions of time related to the wellbeing of  people.

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

Auction sale to close estate of Mary P. Chrystie, dec'd, 23 building plots, also Harlem River water front, near Morris Heights stations, N.Y. Central and N.Y. & Northern railroads : Wednesday, November 22d, 1893, at 12 o'clock noon at no. 111 Broadway, New York Real Estate salesroom : by order of Morris & Steele, attorneys ... New York City /

Street map showing properties to be sold, existing buildings (some with owners' names), and railroad stations.

Synchronization of Heteroclinic Circuits Through Learning in Chains of Neural Motifs

The synchronization of oscillatory activity in networks of neural networks is usually implemented through coupling the state variables describing neuronal dynamics. In this study we discuss another but complementary mechanism based on a learning process with memory. A driver network motif, acting as a teacher, exhibits winner-less competition (WLC) dynamics, while a driven motif, a learner, tunes its internal couplings according to the oscillations observed in the teacher. We show that under appropriate training the learner motif can dynamically copy the coupling pattern of the teacher and thus synchronize oscillations with the teacher. Then, we demonstrate that the replication of the WLC dynamics occurs for intermediate memory lengths only. In a unidirectional chain of N motifs coupled through teacher-learner paradigm the time interval required for pattern replication grows linearly with the chain size, hence the learning process does not blow up and at the end we observe phase synchronized oscillations along the chain. We also show that in a learning chain closed into a ring the network motifs come to a consensus, i.e. to a state with the same connectivity pattern corresponding to the mean initial pattern averaged over all network motifs.

Holistic Design In High-Speed Optical Interconnects

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking.

In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy efficiency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s.

Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW.

Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be –64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.

Cross-talk and regulatory interactions between the essential response regulator RpaB and cyanobacterial circadian clock output

The response regulator RpaB (regulator of phycobilisome associated B), part of an essential two-component system conserved in cyanobacteria that responds to multiple environmental signals, has recently been implicated in the control of cell dimensions and of circadian rhythms of gene expression in the model cyanobacterium Synechococcus elongatus PCC 7942. However, little is known of the molecular mechanisms that underlie RpaB functions. In this study we show that the regulation of phenotypes by RpaB is intimately connected with the activity of RpaA (regulator of phycobilisome associated A), the master regulator of circadian transcription patterns. RpaB affects RpaA activity both through control of gene expression, a function requiring an intact effector domain, and via altering RpaA phosphorylation, a function mediated through the N-terminal receiver domain of RpaB. Thus, both phosphorylation cross-talk and coregulation of target genes play a role in the genetic interactions between the RpaA and RpaB pathways. In addition, RpaB∼P levels appear critical for survival under light:dark cycles, conditions in which RpaB phosphorylation is environmentally driven independent of the circadian clock. We propose that the complex regulatory interactions between the essential and environmentally sensitive NblS-RpaB system and the SasA-RpaA clock output system integrate relevant extra- and intracellular signals to the circadian clock.

Window of Chaotic Delayed Synchronization

We consider a general coupling of two chaotic dynamical systems and we obtain conditions that provide delayed synchronization. We consider four different couplings that satisfy those conditions. We define Window of Delayed Synchronization and we obtain it analytically. We use four different free chaotic dynamics in order to observe numerically the analytically predicted windows for the considered couplings.

Flowering synchronization in hybrid rice parental lines.

The cultivation of hybrid rice is a technology that allows for an increase in grain yield of 30% relative to the grain yield of conventional cultivars. However, the main challenge for this technology is related to seed production, which has high production costs and low seed yields. Therefore, agronomic techniques that could enhance flowering synchrony of parental lines in the field are essential for an efficient production system of hybrid rice seeds. The objective of this work was to study the effects of sowing depth, plant density and fertilization with nitrogen or phosphorus as potential techniques to increase the pollen availability in the field and, consequently, the flowering synchrony between parental lines in the production of hybrid rice seeds. The experiments were conducted during two growing seasons in the Central Region of Brazil. All of the experiments were conducted as a randomized complete block in a split plot scheme; however, the experiment with P fertilization had a factorial design. Our research allow inferring that nitrogen fertilization technique applied to the soil or foliar at the time of panicle differentiation does not affect the time of onset of flowering of rice varieties INTA Puitá CL and L106R, which are potential R lines for the production of hybrid rice. Agronomic techniques of variation in sowing depth, seeding rate and the phosphate fertilization affect the time of onset of flowering from 10 to 19 degree-days, which could represent two days in the crop cycle, for the line L106R. Such techniques constitute potential alternatives for use in hybrid rice seed production systems and could be applied in alternated blocks of R lines in the field to obtain longer periods of pollen availability in the field.