Passive Intermodulation in Distributed Circuits with Cascaded Discrete Nonlinearities

The principle aspects of passive intermodulation (PIM) characterisation in distributed printed circuits with cascaded lumped nonlinearities are presented. Mechanisms of PIM generations have been investigated experimentally and modelled using the formalism of X-parameters. The devised equivalent circuit models are applied to the analysis of microstrip lines with distributed and cascaded lumped sources of nonlinearity. The dynamic measurements have revealed that PIM generation rates in straight and meandered microstrip lines differ and significantly deviate from those expected for the respective discrete sources of nonlinearity. The obtained results indicate that multiple physical sources of nonlinearity contribute to PIM generation in printed circuits. Finally, it is demonstrated that the electrical discontinuities can have significant effect on the overall PIM response of the distributed passive circuits and cause PIM product leakage and parasitic coupling between isolated circuit elements.

Reconfigurable cryptographic RISC microprocessor

This paper describes a novel RISC microprocessor that can be utilised to rapidly develop a reprogrammable and high performance embedded security-processing system in SoC designs. Generic and innovative algorithm-specific instructions have been developed for a wide range of private-key and hash algorithms. To the authors' knowledge, this is the first generic cryptographic microprocessor to be reported in the literature.

Reconfigurable transmitters for software-defined radios

Flexible radio transmitters based on the Software-Defined Radio (SDR) concept are gaining an increased research importance due to the unparalleled proliferation of new wireless standards operating at different frequencies, using dissimilar coding and modulation schemes, and targeted for different ends. In this new wireless communications paradigm, the physical layer of the radio transmitter must be able to support the simultaneous transmission of multi-band, multi-rate, multi-standard signals, which in practice is very hard or very inefficient to implement using conventional approaches. Nevertheless, the last developments in this field include novel all-digital transmitter architectures where the radio datapath is digital from the baseband up to the RF stage. Such concept has inherent high flexibility and poses an important step towards the development of SDR-based transmitters. However, the truth is that implementing such radio for a real world communications scenario is a challenging task, where a few key limitations are still preventing a wider adoption of this concept. This thesis aims exactly to address some of these limitations by proposing and implementing innovative all-digital transmitter architectures with inherent higher flexibility and integration, and where improving important figures of merit, such as coding efficiency, signal-to-noise ratio, usable bandwidth and in-band and out-of-band noise will also be addressed. In the first part of this thesis, the concept of transmitting RF data using an entirely digital approach based on pulsed modulation is introduced. A comparison between several implementation technologies is also presented, allowing to state that FPGAs provide an interesting compromise between performance, power efficiency and flexibility, thus making them an interesting choice as an enabling technology for pulse-based all-digital transmitters. Following this discussion, the fundamental concepts inherent to pulsed modulators, its key advantages, main limitations and typical enhancements suitable for all-digital transmitters are also presented. The recent advances regarding the two most common classes of pulse modulated transmitters, namely the RF and the baseband-level are introduced, along with several examples of state-of-the-art architectures found on the literature. The core of this dissertation containing the main developments achieved during this PhD work is then presented and discussed. The first key contribution to the state-of-the-art presented here consists in the development of a novel ΣΔ-based all-digital transmitter architecture capable of multiband and multi-standard data transmission in a very flexible and integrated way, where the pulsed RF output operating in the microwave frequency range is generated inside a single FPGA device. A fundamental contribution regarding the simultaneous transmission of multiple RF signals is then introduced by presenting and describing novel all-digital transmitter architectures that take advantage of multi-gigabit data serializers available on current high-end FPGAs in order to transmit in a time-interleaved approach multiple independent RF carriers. Further improvements in this design approach allowed to provide a two-stage up-conversion transmitter architecture enabling the fine frequency tuning of concurrent multichannel multi-standard signals. Finally, further improvements regarding two key limitations inherent to current all-digital transmitter approaches are then addressed, namely the poor coding efficiency and the combined high quality factor and tunability requirements of the RF output filter. The followed design approach based on poliphase multipath circuits allowed to create a new FPGA-embedded agile transmitter architecture that significantly improves important figures of merit, such as coding efficiency and SNR, while maintains the high flexibility that is required for supporting multichannel multimode data transmission.

Multi-standard reconfigurable wireless transmitter architectures

The continuous demand for highly efficient wireless transmitter systems has triggered an increased interest in switching mode techniques to handle the required power amplification. The RF carrier amplitude-burst transmitter, i.e. a wireless transmitter chain where a phase-modulated carrier is modulated in amplitude in an on-off mode, according to some prescribed envelope-to-time conversion, such as pulse-width or sigma-delta modulation, constitutes a promising architecture capable of efficiently transmitting signals of highly demanding complex modulation schemes. However, the tested practical implementations present results that are way behind the theoretically advanced promises (perfect linearity and efficiency). My original contribution to knowledge presented in this thesis is the first thorough study and model of the power efficiency and linearity characteristics that can be actually achieved with this architecture. The analysis starts with a brief revision of the theoretical idealized behavior of these switched-mode amplifier systems, followed by the study of the many sources of impairments that appear when the real system is implemented. In particular, a special attention is paid to the dynamic load modulation caused by the often ignored interaction between the narrowband signal reconstruction filter and the usual single-ended switched-mode power amplifier, which, among many other performance impairments, forces a two transistor implementation. The performance of this architecture is clearly explained based on the presented theory, which is supported by simulations and corresponding measured results of a fully working implementation. The drawn conclusions allow the development of a set of design rules for future improvements, one of which is proposed and verified in this thesis. It suggests a significant modification to this traditional architecture, where now the phase modulated carrier is always on – and thus allowing a single transistor implementation – and the amplitude is impressed into the carrier phase according to a bi-phase code.

Q-enhancement with on-chip inductor optimization for reconfigurable Δ-Σ radio-frequency ADC

The paper details on-chip inductor optimization for a reconfigurable continuous-time delta-sigma (Δ-Σ) modulator based radio-frequency analog-to-digital converter. Inductor optimisation enables the Δ-Σ modulator with Q enhanced LC tank circuits employing a single high Q-factor on-chip inductor and lesser quantizer levels thereby reducing the circuit complexity for excess loop delay, power dissipation and dynamic element matching. System level simulations indicate at a Q-factor of 75 Δ- Σ modulator with a 3-level quantizer achieves dynamic ranges of 106, 82 dB and 84 dB for RFID, TETRA, and Galileo over bandwidths of 200 kHz, 10 MHz and 40 MHz respectively.

Multiuser Detection for the Uplink of Prefix-Assisted DS-CDMA Systems Employing Multiple Transmit and Receive Antennas

In this paper we consider the uplink transmission within a DS-CDMA system employing CP-assisted (Cylic Prefix) block transmission techniques combined with spatial multiplexing techniques that require multiple antennas at both the transmitter and the receiver. We present an efficient frequency-domain receiver structure with iterative MUD (MultiUser Detection). The performance of the proposed receiver can be close to the single user matched filter bound, even for fully loaded systems and/or severely time-dispersive channels.

Compact dielectric-filled waveguide filters and diplexers

This paper presents electromagnetic simulations of dielectric-filled rectangular waveguide bandpass filter structures with microstrip to waveguide transitions as well as a diplexer based on such filters for modern wireless systems. The two bandpass filters have been designed and simulated at centre frequencies of 11.85 and 14.25 GHz, respectively. A significant size reduction is achieved through dielectric filling.

Compact high linearity switchable dual-mode microstrip bandpass filters

A compact highly linear microstrip dual-mode electronically switchable filter is presented. The key characteristics of the dual-mode switchable filter are investigated and described. A second order filter design procedure is outlined to facilitate the realisation of Butterworth and Chebyshev functions. The proposed filter was built and tested with NXP pin diode model BAP65-03. The measured and simulated results are in good agreement. The measured insertion loss in the ON state was 3.0 dB the isolation in the OFF state was 45 dB at the centre frequency. An evaluation of filter distortion is presented for digitally modulated 16 QAM and QPSK signals.

Optically reconfigurable E-plane waveguide resonators and filters

This paper presents an optically reconfigurable E-plane waveguide resonator and filter. N-type silicon dice doped with phosphorus is used as the switching element and is connected to the edge of a metallic fin. Illumination of the silicon dice allows realization of a different length of the fin, thus creating a shift in resonant frequency of the structure. Frequency tuning range up to about 5.2% is achieved for the resonator as well as the filter. Measurements on a fabricated optically reconfigurable resonator confirm the accuracy of the design procedure. Measured responses show good agreement with simulation.

Compact tunable bandstop filters using defected microstrip structure for multi-standard wireless systems

A novel compact tunable bandstop filter using Defected Microstrip Structure (DMS) is presented in this paper. The structure utilizes a modified T shaped DMS which helps in miniaturization of the filter. To verify the concept, one such filter was simulated, designed, fabricated and tested. Measurements on a fabricated tunable filter confirm the accuracy of the design procedure. The tuning range of 20% is achieved, ranging from 2.26 GHz to 2.747 GHz. Tuning is achieved by using NXP BB179 varactor diode. A nonlinear distortion evaluation in a tunable filter was experimentally verified. Experimental verification shows the filter is highly linear.

Microstrip antenna array for multiband dedicated short range communications systems

Dedicated Short Range Communications (DSRC) is the key enabling technology for the present and future vehicular communication for various applications, such as safety improvement and traffic jam mitigation. This paper describes the development of a microstrip antenna array for the roadside equipment of a DSRC system, whose characteristics are according with the vehicular communications standards. The proposed antenna, with circular polarization, has a wide bandwidth, enough to cover the current European DSRC 5.8 GHz band and the future 5.9 GHz band for next generation DSRC communications. (C) 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53: 2794-2796, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26394

Design and evaluation of multi-band RF energy harvesting circuits and antennas for WSNs

Radio frequency (RF) energy harvesting is an emerging technology that will enable to drive the next generation of wireless sensor networks (WSNs) without the need of using batteries. In this paper, we present RF energy harvesting circuits specifically developed for GSM bands (900/1800) and a wearable dual-band antenna suitable for possible implementation within clothes for body worn applications. Besides, we address the development and experimental characterization of three different prototypes of a five-stage Dickson voltage multiplier (with match impedance circuit) responsible for harvesting the RF energy. Different printed circuit board (PCB) fabrication techniques to produce the prototypes result in different values of conversion efficiency. Therefore, we conclude that if the PCB fabrication is achieved by means of a rigorous control in the photo-positive method and chemical bath procedure applied to the PCB it allows for attaining better values for the conversion efficiency. All three prototypes (1, 2 and 3) can power supply the IRIS sensor node for RF received powers of -4 dBm, -6 dBm and -5 dBm, and conversion efficiencies of 20, 32 and 26%, respectively. © 2014 IEEE.

Peers' evaluation of a reconfigurable IEEE1451.0-compliant and FPGA-based weblab

It is already more than 10 years that weblabs are seen as important resources to provide the experimental work required in engineering education. Several weblabs have been applied in engineering courses, but there are still unsolved problems related to the development of their infrastructures. For solving some of those problems, it was implemented a weblab with a reconfigurable infrastructure compliant with the IEEE1451.0 Std. and supported by Field Programmable Gate Array (FPGA) technology. This paper presents the referred weblab, and provides and analyses a set of researchers' opinions about the implemented infrastructure, and the adopted methodology for the conduction of real experiments.