Desenvolvimento de um sistema de instrumentação de medição de vibração mecânica em máquina rotativas, em tempo real, embarcado em FPGA

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Development of a CAD system for automatic classification of microcalcifications based on FPGA

This paper presents a Computer Aided Diagnosis (CAD) system that automatically classifies microcalcifications detected on digital mammograms into one of the five types proposed by Michele Le Gal, a classification scheme that allows radiologists to determine whether a breast tumor is malignant or not without the need for surgeries. The developed system uses a combination of wavelets and Artificial Neural Networks (ANN) and is executed on an Altera DE2-115 Development Kit, a kit containing a Field-Programmable Gate Array (FPGA) that allows the system to be smaller, cheaper and more energy efficient. Results have shown that the system was able to correctly classify 96.67% of test samples, which can be used as a second opinion by radiologists in breast cancer early diagnosis. (C) 2013 The Authors. Published by Elsevier B.V.

Reconhecimento de voz para aplicações em automação implementado em FPGA

In many movies of scientific fiction, machines were capable of speaking with humans. However mankind is still far away of getting those types of machines, like the famous character C3PO of Star Wars. During the last six decades the automatic speech recognition systems have been the target of many studies. Throughout these years many technics were developed to be used in applications of both software and hardware. There are many types of automatic speech recognition system, among which the one used in this work were the isolated word and independent of the speaker system, using Hidden Markov Models as the recognition system. The goals of this work is to project and synthesize the first two steps of the speech recognition system, the steps are: the speech signal acquisition and the pre-processing of the signal. Both steps were developed in a reprogrammable component named FPGA, using the VHDL hardware description language, owing to the high performance of this component and the flexibility of the language. In this work it is presented all the theory of digital signal processing, as Fast Fourier Transforms and digital filters and also all the theory of speech recognition using Hidden Markov Models and LPC processor. It is also presented all the results obtained for each one of the blocks synthesized e verified in hardware

Bit-parallel coprocessor for standard ECC-GF(2m) on FPGA

This paper presents the design of a high-speed coprocessor for Elliptic Curve Cryptography over binary Galois Field (ECC- GF(2m)). The purpose of our coprocessor is to accelerate the scalar multiplication performed over elliptic curve points represented by affine coordinates in polynomial basis. Our method consists of using elliptic curve parameters over GF(2163) in accordance with international security requirements to implement a bit-parallel coprocessor on field-programmable gate-array (FPGA). Our coprocessor performs modular inversion by using a process based on the Stein's algorithm. Results are presented and compared to results of other related works. We conclude that our coprocessor is suitable for comparing with any other ECC-hardware proposal, since its speed is comparable to projective coordinate designs.

Natural intracellular peptides can modulate the interactions of mouse brain proteins and thimet oligopeptidase with 14-3-3e and calmodulin

Protein interactions are crucial for most cellular process. Thus, rationally designed peptides that act as competitive assembly inhibitors of protein interactions by mimicking specific, determined structural elements have been extensively used in clinical and basic research. Recently, mammalian cells have been shown to contain a large number of intracellular peptides of unknown function. Here, we investigate the role of several of these natural intracellular peptides as putative modulators of protein interactions that are related to Ca2+-calmodulin (CaM) and 14-3-3 epsilon, which are proteins that are related to the spatial organization of signal transduction within cells. At concentrations of 1-50 mu M, most of the peptides that are investigated in this study modulate the interactions of CaM and 14-3-3 epsilon with proteins from the mouse brain cytoplasm or recombinant thimet oligopeptidase (EP24.15) in vitro, as measured by surface plasmon resonance. One of these peptides (VFDVELL; VFD-7) increases the cytosolic Ca2+ concentration in a dose-dependent manner but only if introduced into HEK293 cells, which suggests a wide biological function of this peptide. Therefore, it is exciting to suggest that natural intracellular peptides are novel modulators of protein interactions and have biological functions within cells.

LALP: a language to program custom FPGA-based acceleration engines

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained with Application-Specific Integrated Circuits, while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers in order to master hardware description languages (HDLs) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Bearing in mind an FPGA available resources, it has been developed LALP (Language for Aggressive Loop Pipelining), a novel language to program FPGA-based accelerators, and its compilation framework, including mapping capabilities. The main ideas behind LALP are to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to allow the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. Those features are particularly useful to implement loop pipelining, a well regarded technique used to accelerate computations in several application domains. This paper describes LALP, and shows how it can be used to achieve high-performance computing solutions.

Triggers per attività di test su fascio di particelle. Realizzazione di un progetto in VHDL e sintetizzazione su FPGA

Progettazione e realizzazione di un dispositivo elettronico con lo scopo di coordinare e sincronizzare la presa dati del beam test del LUCID (CERN, luglio 2009) e tener traccia di tali eventi. Il circuito è stato progettato in linguaggio VHDL, simulato con il programma ModelSim, sintetizzato con il programma Quartus e implementato su un FPGA Cyclone residente su scheda di tipo VME 6U della CAEN. Infine la scheda è stata testata in laboratorio (verificandone il corretto funzionamento) assieme all'intero sistema di presa dati, e confermata per il beam test del LUCID.

Cooperative and reconfigurable telecommunication systems based on FPGA

This work has been realized by the author in his PhD course in Electronics, Computer Science and Telecommunication at the University of Bologna, Faculty of Engineering, Italy. The subject of this thesis regards important channel estimation aspects in wideband wireless communication systems, such as echo cancellation in digital video broadcasting systems and pilot aided channel estimation through an innovative pilot design in Multi-Cell Multi-User MIMO-OFDM network. All the documentation here reported is a summary of years of work, under the supervision of Prof. Oreste Andrisano, coordinator of Wireless Communication Laboratory - WiLab, in Bologna. All the instrumentation that has been used for the characterization of the telecommunication systems belongs to CNR (National Research Council), CNIT (Italian Inter-University Center), and DEIS (Dept. of Electronics, Computer Science, and Systems). From November 2009 to May 2010, the author spent his time abroad, working in collaboration with DOCOMO - Communications Laboratories Europe GmbH (DOCOMO Euro-Labs) in Munich, Germany, in the Wireless Technologies Research Group. Some important scientific papers, submitted and/or published on IEEE journals and conferences have been produced by the author.

Sviluppo di un modulo VHDL per interfacciamento Ethernet-FPGA in applicazioni di high throughput screening

In molti settori della ricerca in campo biologico e biomedico si fa ricorso a tecniche di High Throughput Screening (HTS), tra cui studio dei canali ionici. In questo campo si studia la conduzione di ioni attraverso una membrana cellulare durante fenomeni che durano solo alcuni millisecondi. Allo scopo sono solitamente usati sensori e convertitori A/D ad elevata velocità insieme ad opportune interfacce di comunicazione, ad elevato bit-rate e latenza ridotta. In questa tesi viene descritta l'implementazione di un modulo VHDL per la trasmissione di dati digitali provenienti da un sistema HTS attraverso un controller di rete integrato dotato di un'interfaccia di tipo Ethernet, individuando le possibili ottimizzazioni specifiche per l'applicazione di interesse.

Design and implementation of a novel multi-constellation FPGA-based dual frequency GNSS receiver for space applications

The PhD activity described in the document is part of the Microsatellite and Microsystem Laboratory of the II Faculty of Engineering, University of Bologna. The main objective is the design and development of a GNSS receiver for the orbit determination of microsatellites in low earth orbit. The development starts from the electronic design and goes up to the implementation of the navigation algorithms, covering all the aspects that are involved in this type of applications. The use of GPS receivers for orbit determination is a consolidated application used in many space missions, but the development of the new GNSS system within few years, such as the European Galileo, the Chinese COMPASS and the Russian modernized GLONASS, proposes new challenges and offers new opportunities to increase the orbit determination performances. The evaluation of improvements coming from the new systems together with the implementation of a receiver that is compatible with at least one of the new systems, are the main activities of the PhD. The activities can be divided in three section: receiver requirements definition and prototype implementation, design and analysis of the GNSS signal tracking algorithms, and design and analysis of the navigation algorithms. The receiver prototype is based on a Virtex FPGA by Xilinx, and includes a PowerPC processor. The architecture follows the software defined radio paradigm, so most of signal processing is performed in software while only what is strictly necessary is done in hardware. The tracking algorithms are implemented as a combination of Phase Locked Loop and Frequency Locked Loop for the carrier, and Delay Locked Loop with variable bandwidth for the code. The navigation algorithm is based on the extended Kalman filter and includes an accurate LEO orbit model.

Dispositivi FPGA di ultima generazione: analisi e confronto

Questa tesi si prefissa l’obiettivo di analizzare l'evoluzione dei sistemi FPGA nel corso degli ultimi anni, evidenziando le novità e gli aspetti tecnici più significativi che ogni famiglia ha introdotto. Il primo capitolo avrà il compito di mostrare l’architettura ed il funzionamento generale di un FPGA, cercando di illustrarne le principali caratteristiche. Il secondo capitolo introdurrà i dispositivi FPGA Xilinx e mostrerà le caratteristiche tecniche dei principali dispositivi prodotto dall'azienda. Il terzo capitolo mostrerà invece le caratteristiche tecniche degli FPGA più recenti prodotti da Altera. Il quarto ed ultimo capitolo, invece, metterà a confronto alcuni parametri fondamentali dei dispositivi descritti nell'elaborato.