Host-based P2P flow identification and use in real-time

Data identification is a key task for any Internet Service Provider (ISP) or network administrator. As port fluctuation and encryption become more common in P2P traffic wishing to avoid identification, new strategies must be developed to detect and classify such flows. This paper introduces a new method of separating P2P and standard web traffic that can be applied as part of a data mining process, based on the activity of the hosts on the network. Unlike other research, our method is aimed at classifying individual flows rather than just identifying P2P hosts or ports. Heuristics are analysed and a classification system proposed. The accuracy of the system is then tested using real network traffic from a core internet router showing over 99% accuracy in some cases. We expand on this proposed strategy to investigate its application to real-time, early classification problems. New proposals are made and the results of real-time experiments compared to those obtained in the data mining research. To the best of our knowledge this is the first research to use host based flow identification to determine a flows application within the early stages of the connection.

Hierarchical synthesis of complex DSP functions on FPGAs

SoC systems are now being increasingly constructed using a hierarchy of subsystems or silicon Intellectual Property (IP) cores. The key challenge is to use these cores in a highly efficient manner which can be difficult as the internal core structure may not be known. A design methodology based on synthesizing hierarchical circuit descriptions is presented. The paper employs the MARS synthesis scheduling algorithm within the existing IRIS synthesis flow and details how it can be enhanced to allow for design exploration of IP cores. It is shown that by accessing parameterised expressions for the datapath latencies in the cores, highly efficient FPGA solutions can be achieved. Hardware sharing at both the hierarchical and flattened levels is explored for a normalized lattice filter and results are presented.

Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

Preaching to Princes: John Burgess and George Hakewill in the Royal Pulpit

This article examines a previously unnoticed link between the Puritan John Burgess and the Calvinist conformist George Hakewill. In 1604 Burgess preached a court sermon so outspoken and critical of James I’s religious policy that he was imprisoned. Nearly twenty years later, however, Hakewill chose to incorporate extended passages from Burgess’s sermon into the series of sermons, King David’s vow (1621), preached to Prince Charles’s household. This article considers why Burgess’s sermon became so resonant for Hakewill in the early 1620s and also demonstrates how Hakewill deliberately sought to moderate Burgess’s strident polemic. In so doing the article provides important new evidence for the politically attuned sermon culture at Prince Charles’s court in the early 1620s and also suggests how, as the parameters for clerical conformity shifted in the latter years of James’s reign, Calvinist conformists found a new appeal in the works of moderate Puritans. I

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Prices and Wages in Ireland, 1700-1850

The article presents primary research on rural wages and the prices of agricultural goods and draws conclusions concerning the trend in the living conditions of rural workers in the century before the Great Irish Famine of 1845-1850.

"Producers and Consumers in EU E-Commerce Law by John Dickie, Oxford: Hart Publishing, 2005 (ISBN 1-841-13454-6)"

Book Review