Synthesis and characterization of implants for bone substitutions made of biomedical apatites containing silicon

In the last decades the development of bone substitutes characterized by a superior biomimetism has become of particular interest, owing to the increasing economic and societal impact of the bone diseases. In the present work of research the development of bone substitutes characterized by improved biomimetism, has been faced in a chemical, structural and morphological perspective. From a chemical point of view, it has been developed the synthesis of hydroxyapatite powders, exhibiting multiple ionic substitutions in both cationic and anionic sites, so to simulate the chemical composition of the natural bone. Particular emphasis has been given to the effect of silicon on the chemical-physical and solubility properties of the obtained hydroxyapatites. From a structural point of view, it has been developed the synthesis of ceramic composite materials, based on hydroxyapatite and calcium silicates, employed both as a reinforcing phase, to raise the mechanical strength of the composite compared to hydroxyapatite, and as a bioactive phase, able to increase the bioactivity properties of the whole ceramic. Finally the unique morphological features of the bone were mimicked by taking inspiration by Nature, so that native wood structures were treated in chemical and thermal way to obtain hydroxyapatite porous materials characterized by the same morphology as the native wood. The results obtained in the present work were positive in all the three different areas of investigation, so to cover the three different aspects of biomimetism, chemical, structural and morphological. Anyway, only at the convergence of the three different fields it is possible to find out the best solutions to develop the ideal bone-like scaffold. Thus, the future activity should be devoted to solve the problems at the borderline between the different research lines, which hamper this convergence and in consequence, the achievement of a bone scaffold able to mimic the various aspects exhibited by the bone tissue

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Enabling Blocks for Integrated CMOS UWB Transceivers

The last decades have seen an unrivaled growth and diffusion of mobile telecommunications. Several standards have been developed to this purposes, from GSM mobile phone communications to WLAN IEEE 802.11, providing different services for the the transmission of signals ranging from voice to high data rate digital communications and Digital Video Broadcasting (DVB). In this wide research and market field, this thesis focuses on Ultra Wideband (UWB) communications, an emerging technology for providing very high data rate transmissions over very short distances. In particular the presented research deals with the circuit design of enabling blocks for MB-OFDM UWB CMOS single-chip transceivers, namely the frequency synthesizer and the transmission mixer and power amplifier. First we discuss three different models for the simulation of chargepump phase-locked loops, namely the continuous time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, a phase noise analysis method based upon the time-domain model is introduced and compared to the results obtained by means of the s-domain model. We compare the three models over the simulation of a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems. In the second part, the theoretical analysis is applied to the design of a 60mW 3.4 to 9.2GHz 12 Bands frequency synthesizer for MB-OFDM UWB based on two wide-band PLLs. The design is presented and discussed up to layout level. A test chip has been implemented in TSMC CMOS 90nm technology, measured data is provided. The functionality of the circuit is proved and specifications are met with state-of-the-art area occupation and power consumption. The last part of the thesis deals with the design of a transmission mixer and a power amplifier for MB-OFDM UWB band group 1. The design has been carried on up to layout level in ST Microlectronics 65nm CMOS technology. Main characteristics of the systems are the wideband behavior (1.6 GHz of bandwidth) and the constant behavior over process parameters, temperature and supply voltage thanks to the design of dedicated adaptive biasing circuits.

Applications of High Speed Configurable Logic Devices in Modern Particle Physics Experiments

Several activities were conducted during my PhD activity. For the NEMO experiment a collaboration between the INFN/University groups of Catania and Bologna led to the development and production of a mixed signal acquisition board for the Nemo Km3 telescope. The research concerned the feasibility study for a different acquisition technique quite far from that adopted in the NEMO Phase 1 telescope. The DAQ board that we realized exploits the LIRA06 front-end chip for the analog acquisition of anodic an dynodic sources of a PMT (Photo-Multiplier Tube). The low-power analog acquisition allows to sample contemporaneously multiple channels of the PMT at different gain factors in order to increase the signal response linearity over a wider dynamic range. Also the auto triggering and self-event-classification features help to improve the acquisition performance and the knowledge on the neutrino event. A fully functional interface towards the first level data concentrator, the Floor Control Module, has been integrated as well on the board, and a specific firmware has been realized to comply with the present communication protocols. This stage of the project foresees the use of an FPGA, a high speed configurable device, to provide the board with a flexible digital logic control core. After the validation of the whole front-end architecture this feature would be probably integrated in a common mixed-signal ASIC (Application Specific Integrated Circuit). The volatile nature of the configuration memory of the FPGA implied the integration of a flash ISP (In System Programming) memory and a smart architecture for a safe remote reconfiguration of it. All the integrated features of the board have been tested. At the Catania laboratory the behavior of the LIRA chip has been investigated in the digital environment of the DAQ board and we succeeded in driving the acquisition with the FPGA. The PMT pulses generated with an arbitrary waveform generator were correctly triggered and acquired by the analog chip, and successively they were digitized by the on board ADC under the supervision of the FPGA. For the communication towards the data concentrator a test bench has been realized in Bologna where, thanks to a lending of the Roma University and INFN, a full readout chain equivalent to that present in the NEMO phase-1 was installed. These tests showed a good behavior of the digital electronic that was able to receive and to execute command imparted by the PC console and to answer back with a reply. The remotely configurable logic behaved well too and demonstrated, at least in principle, the validity of this technique. A new prototype board is now under development at the Catania laboratory as an evolution of the one described above. This board is going to be deployed within the NEMO Phase-2 tower in one of its floors dedicated to new front-end proposals. This board will integrate a new analog acquisition chip called SAS (Smart Auto-triggering Sampler) introducing thus a new analog front-end but inheriting most of the digital logic present in the current DAQ board discussed in this thesis. For what concern the activity on high-resolution vertex detectors, I worked within the SLIM5 collaboration for the characterization of a MAPS (Monolithic Active Pixel Sensor) device called APSEL-4D. The mentioned chip is a matrix of 4096 active pixel sensors with deep N-well implantations meant for charge collection and to shield the analog electronics from digital noise. The chip integrates the full-custom sensors matrix and the sparsifification/readout logic realized with standard-cells in STM CMOS technology 130 nm. For the chip characterization a test-beam has been set up on the 12 GeV PS (Proton Synchrotron) line facility at CERN of Geneva (CH). The collaboration prepared a silicon strip telescope and a DAQ system (hardware and software) for data acquisition and control of the telescope that allowed to store about 90 million events in 7 equivalent days of live-time of the beam. My activities concerned basically the realization of a firmware interface towards and from the MAPS chip in order to integrate it on the general DAQ system. Thereafter I worked on the DAQ software to implement on it a proper Slow Control interface of the APSEL4D. Several APSEL4D chips with different thinning have been tested during the test beam. Those with 100 and 300 um presented an overall efficiency of about 90% imparting a threshold of 450 electrons. The test-beam allowed to estimate also the resolution of the pixel sensor providing good results consistent with the pitch/sqrt(12) formula. The MAPS intrinsic resolution has been extracted from the width of the residual plot taking into account the multiple scattering effect.

Physical models for numerical simulation of Si-based nanoscale FETs and sensors

To continuously improve the performance of metal-oxide-semiconductor field-effect-transistors (MOSFETs), innovative device architectures, gate stack engineering and mobility enhancement techniques are under investigation. In this framework, new physics-based models for Technology Computer-Aided-Design (TCAD) simulation tools are needed to accurately predict the performance of upcoming nanoscale devices and to provide guidelines for their optimization. In this thesis, advanced physically-based mobility models for ultrathin body (UTB) devices with either planar or vertical architectures such as single-gate silicon-on-insulator (SOI) field-effect transistors (FETs), double-gate FETs, FinFETs and silicon nanowire FETs, integrating strain technology and high-κ gate stacks are presented. The effective mobility of the two-dimensional electron/hole gas in a UTB FETs channel is calculated taking into account its tensorial nature and the quantization effects. All the scattering events relevant for thin silicon films and for high-κ dielectrics and metal gates have been addressed and modeled for UTB FETs on differently oriented substrates. The effects of mechanical stress on (100) and (110) silicon band structures have been modeled for a generic stress configuration. Performance will also derive from heterogeneity, coming from the increasing diversity of functions integrated on complementary metal-oxide-semiconductor (CMOS) platforms. For example, new architectural concepts are of interest not only to extend the FET scaling process, but also to develop innovative sensor applications. Benefiting from properties like large surface-to-volume ratio and extreme sensitivity to surface modifications, silicon-nanowire-based sensors are gaining special attention in research. In this thesis, a comprehensive analysis of the physical effects playing a role in the detection of gas molecules is carried out by TCAD simulations combined with interface characterization techniques. The complex interaction of charge transport in silicon nanowires of different dimensions with interface trap states and remote charges is addressed to correctly reproduce experimental results of recently fabricated gas nanosensors.

Progetto e realizzazione di riferimenti in tensione simmetrici in tecnologia CMOS

La tesi tratta del progetto e della realizzazione di un riferimento in tensione simmetrico e stabile in temperatura, realizzato in tecnologia CMOS. Nella progettazione analogica ad alta precisione ha assunto sempre più importanza il problema della realizzazione di riferimenti in tensione stabili in temperatura. Nella maggior parte dei casi vengono presentati Bandgap, ovvero riferimenti in tensione che sfruttano l'andamento in temperatura dell'energy gap del silicio al fine di ottenere una tensione costante in un ampio range di temperatura. Tale architettura risulta utile nei sistemi ad alimentazione singola compresa fra 0 e Vdd essendo in grado di generare una singola tensione di riferimento del valore tipico di 1.2V. Nella tesi viene presentato un riferimento in tensione in grado di offrire le stesse prestazioni di un Bandgap per quanto riguarda la variazione in temperatura ma in grado di lavorare sia in sistemi ad alimentazione singola che ad alimentazione duale. Il circuito proposto e' in grado di generare due tensioni, simmetriche rispetto a un riferimento dato, del valore nominale di ±450mV. All'interno della tesi viene descritto il progetto di due diverse architetture, entrambe in grado di generare le tensioni con le specifiche richieste. Le due architetture sono poi state confrontate analizzando in particolare la stabilità in temperatura, la potenza dissipata, il PSRR (Power Supply Rejection Ratio) e la simmetria delle tensioni generate. Al termine dell'analisi è stato poi implementato su silicio il circuito che garantiva le prestazioni migliori. In sede di disegno del layout su silicio sono stati affrontati i problemi derivanti dall'adattamento dei componenti al fine di ottenere una maggiore insensibilità del circuito stesso alle incertezze legate al processo di realizzazione. Infine sono state effettuate le misurazioni attraverso una probe station a 4 sonde per verificare il corretto funzionamento del circuito e le sue prestazioni.

The incomplete ionization of substitutional dopants in Silicon Carbide

This thesis analyzes theoretically and computationally the phenomenon of partial ionization of the substitutional dopants in Silicon Carbide at thermal equilibrium. It is based on the solution of the charge neutrality equation and takes into account the following phenomena: several energy levels in the bandgap; Fermi-Dirac statistics for free carriers; screening effects on the dopant ionization energies; the formation of impurity bands. A self-consistent model and a corresponding simulation software have been realized. A preliminary comparison of our calculations with existing experimental results is carried out.

Silicon-containing block copolymers with well-defined, branched architectures

In the past decade, block copolymers (BCPs) have attracted increasing scientific and technological interest because of their inherent capability to spontaneously self-assemble into ordered arrays of nanostructures. The importance of nanostructures in a number of applications has fostered the need for well-defined, complex macromolecular architectures. In this thesis, the influence of macromolecular architecture on the bulk morphologies of novel linear-hyperbranched and linear brush-like diblock copolymer structure is investigated. An innovative, generally applicable strategy for the preparation of these defined diblock copolymers, consisting of linear polystyrene and branched polycarbosilane blocks, is demonstrated. Furthermore, complete characterization and solid-state morphological studies are provided. Finally, the concept is extended to linear-hyperbrached and linear brush-like polyalkoxysilanes. A shift of the classical phase boundaries to higher PS weight fractions as well as the appearance of new morphologies confirms the dramatic effect that polymer topology has on the morphology of BCPs.

Advanced Numerical Simulation of Silicon-Based Solar Cells

Photovoltaic (PV) conversion is the direct production of electrical energy from sun without involving the emission of polluting substances. In order to be competitive with other energy sources, cost of the PV technology must be reduced ensuring adequate conversion efficiencies. These goals have motivated the interest of researchers in investigating advanced designs of crystalline silicon solar (c-Si) cells. Since lowering the cost of PV devices involves the reduction of the volume of semiconductor, an effective light trapping strategy aimed at increasing the photon absorption is required. Modeling of solar cells by electro-optical numerical simulation is helpful to predict the performance of future generations devices exhibiting advanced light-trapping schemes and to provide new and more specific guidelines to industry. The approaches to optical simulation commonly adopted for c-Si solar cells may lead to inaccurate results in case of thin film and nano-stuctured solar cells. On the other hand, rigorous solvers of Maxwell equations are really cpu- and memory-intensive. Recently, in optical simulation of solar cells, the RCWA method has gained relevance, providing a good trade-off between accuracy and computational resources requirement. This thesis is a contribution to the numerical simulation of advanced silicon solar cells by means of a state-of-the-art numerical 2-D/3-D device simulator, that has been successfully applied to the simulation of selective emitter and the rear point contact solar cells, for which the multi-dimensionality of the transport model is required in order to properly account for all physical competing mechanisms. In the second part of the thesis, the optical problems is discussed. Two novel and computationally efficient RCWA implementations for 2-D simulation domains as well as a third RCWA for 3-D structures based on an eigenvalues calculation approach have been presented. The proposed simulators have been validated in terms of accuracy, numerical convergence, computation time and correctness of results.

Advanced CMOS Interfaces for Bio-Nanosensors

The improvement of devices provided by Nanotechnology has put forward new classes of sensors, called bio-nanosensors, which are very promising for the detection of biochemical molecules in a large variety of applications. Their use in lab-on-a-chip could gives rise to new opportunities in many fields, from health-care and bio-warfare to environmental and high-throughput screening for pharmaceutical industry. Bio-nanosensors have great advantages in terms of cost, performance, and parallelization. Indeed, they require very low quantities of reagents and improve the overall signal-to-noise-ratio due to increase of binding signal variations vs. area and reduction of stray capacitances. Additionally, they give rise to new challenges, such as the need to design high-performance low-noise integrated electronic interfaces. This thesis is related to the design of high-performance advanced CMOS interfaces for electrochemical bio-nanosensors. The main focus of the thesis is: 1) critical analysis of noise in sensing interfaces, 2) devising new techniques for noise reduction in discrete-time approaches, 3) developing new architectures for low-noise, low-power sensing interfaces. The manuscript reports a multi-project activity focusing on low-noise design and presents two developed integrated circuits (ICs) as examples of advanced CMOS interfaces for bio-nanosensors. The first project concerns low-noise current-sensing interface for DC and transient measurements of electrophysiological signals. The focus of this research activity is on the noise optimization of the electronic interface. A new noise reduction technique has been developed so as to realize an integrated CMOS interfaces with performance comparable with state-of-the-art instrumentations. The second project intends to realize a stand-alone, high-accuracy electrochemical impedance spectroscopy interface. The system is tailored for conductivity-temperature-depth sensors in environmental applications, as well as for bio-nanosensors. It is based on a band-pass delta-sigma technique and combines low-noise performance with low-power requirements.

Manufacturing and characterization of amorphous silicon alloys passivation layers for silicon hetero-junction solar cells

Nel presente lavoro di tesi magistrale sono stati depositati e caratterizzati film sottili (circa 10 nm) di silicio amorfo idrogenato (a-Si:H), studiando in particolare leghe a basso contenuto di ossigeno e carbonio. Tali layer andranno ad essere implementati come strati di passivazione per wafer di Si monocristallino in celle solari ad eterogiunzione HIT (heterojunctions with intrinsic thin layer), con le quali recentemente è stato raggiunto il record di efficienza pari a 24.7% . La deposizione è avvenuta mediante PECVD (plasma enhanced chemical vapour deposition). Tecniche di spettroscopia ottica, come FT-IR (Fourier transform infrared spectroscopy) e SE (spettroscopic ellipsometry) sono state utilizzate per analizzare le configurazioni di legami eteronucleari (Si-H, Si-O, Si-C) e le proprietà strutturali dei film sottili: un nuovo metodo è stato implementato per calcolare i contenuti atomici di H, O e C da misure ottiche. In tal modo è stato possibile osservare come una bassa incorporazione (< 10%) di ossigeno e carbonio sia sufficiente ad aumentare la porosità ed il grado di disordine a lungo raggio del materiale: relativamente a quest’ultimo aspetto, è stata sviluppata una nuova tecnica per determinare dagli spettri ellisometrici l’energia di Urbach, che esprime la coda esponenziale interna al gap in semiconduttori amorfi e fornisce una stima degli stati elettronici in presenza di disordine reticolare. Nella seconda parte della tesi sono stati sviluppati esperimenti di annealing isocrono, in modo da studiare i processi di cristallizzazione e di effusione dell’idrogeno, correlandoli con la degradazione delle proprietà optoelettroniche. L’analisi dei differenti risultati ottenuti studiando queste particolari leghe (a-SiOx e a-SiCy) ha permesso di concludere che solo con una bassa percentuale di ossigeno o carbonio, i.e. < 3.5 %, è possibile migliorare la risposta termica dello specifico layer, ritardando i fenomeni di degradazione di circa 50°C.