Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

High-radix systolic modular multiplication on reconfigurable hardware

The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high-radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs. Unlike previous approaches, each processing element (PE) comprises both an adder and a multiplier. The inclusion of a multiplier in the PE means that the need to pre-compute or store any multiples of the operands is avoided. This also allows very high-radix implementations to be realised, further reducing the amount of clock cycles per modular multiplication, while still maintaining a competitive critical delay. For demonstrative purposes, 512-bit and 1024-bit FPGA implementations using radices of 2(8) and 2(16) are presented. The subsequent throughput rates are the fastest reported to date.

Limits of Dissent, Perils of Activism: Spaces of Resistance and the New Security Logic

On 26 December 2003 an Israeli activist was shot by the Israeli Army while he was participating in a demonstration organized by Anarchists Against the Wall (AAtW) in the West Bank. This was the first time Israeli Soldiers have deliberately shot live bullets at a Jewish-Israeli activist. This paper is an attempt to understand the set of conditions, the enveloping frameworks, and the new discourses that have made this event, and similar shootings that soon followed, possible. Situating the actions of AAtW within a much wider context of securitization—of identities, movements, and bodies—we examine strategies of resistance which are deployed in highly securitized public spaces. We claim that an unexpected matrix of identity in which abnormality is configured as security threat render the bodies of activists especially precarious. The paper thus provides an account of the new rationales of security technologies and tactics which increasingly govern public spaces.

Reconfigurable frequency selective surfaces with interleaved spiral slots

A new type of active frequency selective surface (AFSS) is proposed to realise a voltage controlled bi-state (transparent and reflecting) response at the specified frequencies. The bi-state switching is achieved by combining a passive array of interleaved spiral slots in conducting screens and active dipole arrays with integrated pin diodes at the opposite sides of a thin dielectric substrate. Simulation results show that such active surfaces have high isolation between the transparency and reflection states, while retaining the merits of substantially sub-wavelength response of the unit cell and large fractional bandwidths (FBWs) inherent to the original passive interwoven spiral arrays. Potential applications include reconfigurable and controllable electromagnetic architecture of buildings.

Taking Baby Steps in Molecular Logic-based Computation

Molecular logic-based computation is a broad umbrella covering molecular sensors at its simplest level and logic gate arrays involving steadily increasing levels of parallel and serial integration. The fluorescent PET(photoinduced electron transfer) switching principle remains a loyal servant of this entire field. Applications arise from the convenient operation of molecular information processors in very small spaces.

Building pH Sensors into Paper-based Small-molecular Logic Sys-tems for Very Simple Detection of Edges of Objects

Genetically-engineered bacteria and reactive DNA networks detect edges of objects, as done in our retinas and as also found within computer vision. We now demonstrate that simple molecular logic systems (a combination of a pH sensor, a photo acid generator and a pH buffer spread on paper) without any organization can achieve this relatively complex computational goal with good-fidelity. This causes a jump in the complexity achievable by molecular logic-based computation and extends its applicability. The molecular species involved in light dose-driven 'off-on-off' fluorescence is diverted in the ‘on’ state by proton diffusion from irradiated to unirradiated regions where it escapes a strong quencher, thus visualizing the edge of a mask.

Assembling a consistent set of sentences in relational probabilistic logic with stochastic independence

We examine the representation of judgements of stochastic independence in probabilistic logics. We focus on a relational logic where (i) judgements of stochastic independence are encoded by directed acyclic graphs, and (ii) probabilistic assessments are flexible in the sense that they are not required to specify a single probability measure. We discuss issues of knowledge representation and inference that arise from our particular combination of graphs, stochastic independence, logical formulas and probabilistic assessments.

Probabilistic logic with independence

This paper investigates probabilistic logics endowed with independence relations. We review propositional probabilistic languages without and with independence. We then consider graph-theoretic representations for propositional probabilistic logic with independence; complexity is analyzed, algorithms are derived, and examples are discussed. Finally, we examine a restricted first-order probabilistic logic that generalizes relational Bayesian networks.

A comparison of merging operators in possibilistic logic.

In this paper, we compare merging operators in possibilistic logic. We rst propose an approach to evaluating the discriminating power of a merging operator. After that, we analyze the computational complexity of existing possibilistic merging operators. Finally, we consider the compatibility of possibilistic merging operators with propositional merging operators.