915 resultados para Two-level scheduling and optimization


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A shortage of medical personnel has become a critical problem for developing countries attempting to expand the provision of medical services for the poor. In order to highlight the driving forces determining the international allocation of medical personnel, the cases of four countries, namely the Philippines and South Africa as source countries and Saudi Arabia and the United Kingdom as destination countries, are examined. The paper concludes that changes in demand generated in major destination countries determine the international allocation of medical personnel at least in the short run. Major destination countries often alter their policies on how many medical staff they can accept, and from where, while source countries are required to make appropriate responses to the changes in demand.

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This paper uses firm-level data to examine the impact of foreign chemical safety regulations such as RoHS and REACH on the production costs and export performance of firms in Malaysia and Vietnam. This paper also investigates the role of global value chains in enhancing the likelihood that a firm complies with RoHS and REACH. We find that in addition to the initial setup costs for compliance, EU RoHS (REACH) implementation imposes on firms additional variable production costs by requiring additional labor and capital expenditures of around 57% (73%) of variable costs. We also find that compliance with RoHS and REACH significantly increases the probability of export and that compliance with EU RoHS and REACH helps firms enter a greater variety of countries. Furthermore, firms participating in global value chains have higher compliance with RoHS and REACH regulations, regardless of whether the firm is directly exporting, when the firm operates in upstream or downstream industries of the countries' supply chain.

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We present a novel framework for encoding latency analysis of arbitrary multiview video coding prediction structures. This framework avoids the need to consider an specific encoder architecture for encoding latency analysis by assuming an unlimited processing capacity on the multiview encoder. Under this assumption, only the influence of the prediction structure and the processing times have to be considered, and the encoding latency is solved systematically by means of a graph model. The results obtained with this model are valid for a multiview encoder with sufficient processing capacity and serve as a lower bound otherwise. Furthermore, with the objective of low latency encoder design with low penalty on rate-distortion performance, the graph model allows us to identify the prediction relationships that add higher encoding latency to the encoder. Experimental results for JMVM prediction structures illustrate how low latency prediction structures with a low rate-distortion penalty can be derived in a systematic manner using the new model.

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The research work that here is summarized, it is classed on the area of dynamics and measures of railway safety, specifically in the study of the influence of the cross wind on the high-speed trains as well as the study of new mitigation measures like wind breaking structures or wind fences, with optimized shapes. The work has been developed in the Research Center in Rail Technology (CITEF), and supported by the Universidad Politécnica de Madrid, Spain.

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We present a tutorial overview of Ciaopp, the Ciao system preprocessor. Ciao is a public-domain, next-generation logic programming system, which subsumes ISO-Prolog and is specifically designed to a) be highly extensible via librarles and b) support modular program analysis, debugging, and optimization. The latter tasks are performed in an integrated fashion by Ciaopp. Ciaopp uses modular, incremental abstract interpretation to infer properties of program predicates and literals, including types, variable instantiation properties (including modes), non-failure, determinacy, bounds on computational cost, bounds on sizes of terms in the program, etc. Using such analysis information, Ciaopp can find errors at compile-time in programs and/or perform partial verification. Ciaopp checks how programs cali system librarles and also any assertions present in the program or in other modules used by the program. These assertions are also used to genérate documentation automatically. Ciaopp also uses analysis information to perform program transformations and optimizations such as múltiple abstract specialization, parallelization (including granularity control), and optimization of run-time tests for properties which cannot be checked completely at compile-time. We illustrate "hands-on" the use of Ciaopp in all these tasks. By design, Ciaopp is a generic tool, which can be easily tailored to perform these and other tasks for different LP and CLP dialects.

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In this paper, we examine the issue of memory management in the parallel execution of logic programs. We concentrate on non-deterministic and-parallel schemes which we believe present a relatively general set of problems to be solved, including most of those encountered in the memory management of or-parallel systems. We present a distributed stack memory management model which allows flexible scheduling of goals. Previously proposed models (based on the "Marker model") are lacking in that they impose restrictions on the selection of goals to be executed or they may require consume a large amount of virtual memory. This paper first presents results which imply that the above mentioned shortcomings can have significant performance impacts. An extension of the Marker Model is then proposed which allows flexible scheduling of goals while keeping (virtual) memory consumption down. Measurements are presented which show the advantage of this solution. Methods for handling forward and backward execution, cut and roll back are discussed in the context of the proposed scheme. In addition, the paper shows how the same mechanism for flexible scheduling can be applied to allow the efficient handling of the very general form of suspension that can occur in systems which combine several types of and-parallelism and more sophisticated methods of executing logic programs. We believe that the results are applicable to many and- and or-parallel systems.

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In previous works we demonstrated the benefits of using micro–nano patterning materials to be used as bio-photonic sensing cells (BICELLs), referred as micro–nano photonic structures having immobilized bioreceptors on its surface with the capability of recognizing the molecular binding by optical transduction. Gestrinone/anti-gestrinone and BSA/anti-BSA pairs were proven under different optical configurations to experimentally validate the biosensing capability of these bio-sensitive photonic architectures. Moreover, Three-Dimensional Finite Difference Time Domain (FDTD) models were employed for simulating the optical response of these structures. For this article, we have developed an effective analytical simulation methodology capable of simulating complex biophotonic sensing architectures. This simulation method has been tested and compared with previous experimental results and FDTD models. Moreover, this effective simulation methodology can be used for efficiently design and optimize any structure as BICELL. In particular for this article, six different BICELL's types have been optimized. To carry out this optimization we have considered three figures of merit: optical sensitivity, Q-factor and signal amplitude. The final objective of this paper is not only validating a suitable and efficient optical simulation methodology but also demonstrating the capability of this method for analyzing the performance of a given number of BICELLs for label-free biosensing.

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Esta tesis presenta un novedoso marco de referencia para el análisis y optimización del retardo de codificación y descodificación para vídeo multivista. El objetivo de este marco de referencia es proporcionar una metodología sistemática para el análisis del retardo en codificadores y descodificadores multivista y herramientas útiles en el diseño de codificadores/descodificadores para aplicaciones con requisitos de bajo retardo. El marco de referencia propuesto caracteriza primero los elementos que tienen influencia en el comportamiento del retardo: i) la estructura de predicción multivista, ii) el modelo hardware del codificador/descodificador y iii) los tiempos de proceso de cuadro. En segundo lugar, proporciona algoritmos para el cálculo del retardo de codificación/ descodificación de cualquier estructura arbitraria de predicción multivista. El núcleo de este marco de referencia consiste en una metodología para el análisis del retardo de codificación/descodificación multivista que es independiente de la arquitectura hardware del codificador/descodificador, completada con un conjunto de modelos que particularizan este análisis del retardo con las características de la arquitectura hardware del codificador/descodificador. Entre estos modelos, aquellos basados en teoría de grafos adquieren especial relevancia debido a su capacidad de desacoplar la influencia de los diferentes elementos en el comportamiento del retardo en el codificador/ descodificador, mediante una abstracción de su capacidad de proceso. Para revelar las posibles aplicaciones de este marco de referencia, esta tesis presenta algunos ejemplos de su utilización en problemas de diseño que afectan a codificadores y descodificadores multivista. Este escenario de aplicación cubre los siguientes casos: estrategias para el diseño de estructuras de predicción que tengan en consideración requisitos de retardo además del comportamiento tasa-distorsión; diseño del número de procesadores y análisis de los requisitos de velocidad de proceso en codificadores/ descodificadores multivista dado un retardo objetivo; y el análisis comparativo del comportamiento del retardo en codificadores multivista con diferentes capacidades de proceso e implementaciones hardware. ABSTRACT This thesis presents a novel framework for the analysis and optimization of the encoding and decoding delay for multiview video. The objective of this framework is to provide a systematic methodology for the analysis of the delay in multiview encoders and decoders and useful tools in the design of multiview encoders/decoders for applications with low delay requirements. The proposed framework characterizes firstly the elements that have an influence in the delay performance: i) the multiview prediction structure ii) the hardware model of the encoder/decoder and iii) frame processing times. Secondly, it provides algorithms for the computation of the encoding/decoding delay of any arbitrary multiview prediction structure. The core of this framework consists in a methodology for the analysis of the multiview encoding/decoding delay that is independent of the hardware architecture of the encoder/decoder, which is completed with a set of models that particularize this delay analysis with the characteristics of the hardware architecture of the encoder/decoder. Among these models, the ones based in graph theory acquire special relevance due to their capacity to detach the influence of the different elements in the delay performance of the encoder/decoder, by means of an abstraction of its processing capacity. To reveal possible applications of this framework, this thesis presents some examples of its utilization in design problems that affect multiview encoders and decoders. This application scenario covers the following cases: strategies for the design of prediction structures that take into consideration delay requirements in addition to the rate-distortion performance; design of number of processors and analysis of processor speed requirements in multiview encoders/decoders given a target delay; and comparative analysis of the encoding delay performance of multiview encoders with different processing capabilities and hardware implementations.

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We present a novel framework for the analysis and optimization of encoding latency for multiview video. Firstly, we characterize the elements that have an influence in the encoding latency performance: (i) the multiview prediction structure and (ii) the hardware encoder model. Then, we provide algorithms to find the encoding latency of any arbitrary multiview prediction structure. The proposed framework relies on the directed acyclic graph encoder latency (DAGEL) model, which provides an abstraction of the processing capacity of the encoder by considering an unbounded number of processors. Using graph theoretic algorithms, the DAGEL model allows us to compute the encoding latency of a given prediction structure, and determine the contribution of the prediction dependencies to it. As an example of DAGEL application, we propose an algorithm to reduce the encoding latency of a given multiview prediction structure up to a target value. In our approach, a minimum number of frame dependencies are pruned, until the latency target value is achieved, thus minimizing the degradation of the rate-distortion performance due to the removal of the prediction dependencies. Finally, we analyze the latency performance of the DAGEL derived prediction structures in multiview encoders with limited processing capacity.

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After a criticism on today’s model for electrical noise in resistors, we pass to use a Quantum-compliant model based on the discreteness of electrical charge in a complex Admittance. From this new model we show that carrier drift viewed as charged particle motion in response to an electric field is unlike to occur in bulk regions of Solid-State devices where carriers react as dipoles against this field. The absence of the shot noise that charges drifting in resistors should produce and the evolution of the Phase Noise with the active power existing in the resonators of L-C oscillators, are two effects added in proof for this conduction model without carrier drift where the resistance of any two-terminal device becomes discrete and has a minimum value per carrier that is the Quantum resistance RK/(2pi)

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It has been proposed that the use of self-assembled quantum dot (QD) arrays can break the Shockley-Queisser efficiency limit by extending the absorption of solar cells into the low-energy photon range while preserving their output voltage. This would be possible if the infrared photons are absorbed in the two sub-bandgap QD transitions simultaneously and the energy of two photons is added up to produce one single electron-hole pair, as described by the intermediate band model. Here, we present an InAs/Al 0.25Ga 0.75As QD solar cell that exhibits such electrical up-conversion of low-energy photons. When the device is monochromatically illuminated with 1.32 eV photons, open-circuit voltages as high as 1.58 V are measured (for a total gap of 1.8 eV). Moreover, the photocurrent produced by illumination with photons exciting the valence band to intermediate band (VB-IB) and the intermediate band to conduction band (IB-CB) transitions can be both spectrally resolved. The first corresponds to the QD inter-band transition and is observable for photons of energy mayor que 1 eV, and the later corresponds to the QD intra-band transition and peaks around 0.5 eV. The voltage up-conversion process reported here for the first time is the key to the use of the low-energy end of the solar spectrum to increase the conversion efficiency, and not only the photocurrent, of single-junction photovoltaic devices. In spite of the low absorption threshold measured in our devices - 0.25 eV - we report open-circuit voltages at room temperature as high as 1.12 V under concentrated broadband illumination.