Analysis and design of split-capacitor resistive-inductive passive damping for LCL filters in grid-connected inverters

Grid-connected inverters require a third-order LCL filter to meet standards such as the IEEE Std. 519-1992 while being compact and cost-effective. LCL filter introduces resonance, which needs to be damped through active or passive methods. Passive damping schemes have less control complexity and are more reliable. This study explores the split-capacitor resistive-inductive (SC-RL) passive damping scheme. The SC-RL damped LCL filter is modelled using state space approach. Using this model, the power loss and damping are analysed. Based on the analysis, the SC-RL scheme is shown to have lower losses than other simpler passive damping methods. This makes the SC-RL scheme suitable for high power applications. A method for component selection that minimises the power loss in the damping resistors while keeping the system well damped is proposed. The design selection takes into account the influence of switching frequency, resonance frequency and the choice of inductance and capacitance values of the filter on the damping component selection. The use of normalised parameters makes it suitable for a wide range of design applications. Analytical results show the losses and quality factor to be in the range of 0.05-0.1% and 2.0-2.5, respectively, which are validated experimentally.

Common-Mode and Differential-Mode Active Damping for PWM Rectifiers

Modern pulse-width-modulated (PWM) rectifiers use LC L filters that can be applied in both the common mode and differential mode to obtain high-performance filtering. Interaction between the passive L and C components in the filter leads to resonance oscillations. These oscillations need to be damped either by the passive damping or active damping. The passive damping increases power loss and can reduce the effectiveness of the filter. Methods of active damping, using control strategy, are lossless while maintaining the effectiveness of the filters. In this paper, an active damping strategy is proposed to damp the oscillations in both line-to-line and line-to-ground. An approach based on pole placement by the state feedback is used to actively damp both the differential-and common-mode filter oscillations. Analytical expressions for the state-feedback controller gains are derived for both continuous and discrete-time model of the filter. Tradeoff in selection of the active damping gain on the lower order power converter harmonics is analyzed using a weighted admittance function. Experimental results on a 10-kVA laboratory prototype PWM rectifier are presented. The results validate the effectiveness of the active damping method, and the tradeoff in the settings of the damping gain.

Hysteresis current controller for a general n-level inverter fed drive with online current error boundary computation and nearly constant switching frequency

A space vector-based hysteresis current controller for any general n-level three phase inverter fed induction motor drive is proposed in this study. It offers fast dynamics, inherent overload protection and low harmonic distortion for the phase voltages and currents. The controller performs online current error boundary calculations and a nearly constant switching frequency is obtained throughout the linear modulation range. The proposed scheme uses only the adjacent voltage vectors of the present sector, similar to space vector pulse-width modulation and exhibits fast dynamic behaviour under different transient conditions. The steps involved in the boundary calculation include the estimation of phase voltages from the current ripple, computation of switching time and voltage error vectors. Experimental results are given to show the performance of the drive at various speeds, effect of sudden change of the load, acceleration, speed reversal and validate the proposed advantages.

Space-Vector-Based Hybrid Pulsewidth Modulation Techniques for a Three-Level Inverter

Novel switching sequences have been proposed recently for a neutral-point-clamped three-level inverter, controlled effectively as an equivalent two-level inverter. It is shown that the four novel sequences can be grouped into two pairs of sequences. Using each pair of sequences, a hybrid pulsewidth modulation (PWM) technique is proposed, which deploys the two sequences in appropriate spatial regions to reduce the current ripple. Further, a third hybrid PWM technique is proposed which uses all the five sequences (including the conventional sequence) in appropriate spatial regions. Each proposed hybrid PWM is shown, both analytically and experimentally, to outperform its constituent PWM methods in terms of harmonic distortion. In particular, the third proposed hybrid PWM reduces the total harmonic distortion considerably at low- and high-speed ranges of a constant volts-per-hertz induction motor drive, compared to centered space vector PWM.

A VARIABLE SWITCHING FREQUENCY PWM TECHNIQUE FOR INVERTER-FED INDUCTION MOTOR TO ACHIEVE SPREAD SPECTRUM

Voltage Source Inverter (VSI) fed induction motors are widely used in variable speed applications. For inverters using fixed switching frequency PWM, the output harmonic spectra are located at a few discrete frequencies. The ac motordrives powered by these inverters cause acoustic noise. This paper proposes a new variable switching frequency pwm technique and compares its performance with constant switching frequency pwm technique. It is shown that the proposed technique leads to spread spectra of voltages and currents. Also this technique ensures that no lower order harmonics are present and the current THD is comparable to that of fixed switching frequency PWM and is even better for higher modulation indices.

A Low-Cost System for Measurement and Spectral Analysis of Motor Acoustic Noise

Workplace noise has become one of the major issues in industry not only because of workers’ health but also due to safety. Electric motors, particularly, inverter fed induction motors emit objectionably high levels of noise. This has led to the emergence of a research area, concerned with measurement and mitigation of the acoustic noise. This paper presents a lowcost option for measurement and spectral analysis of acoustic noise emitted by electric motors. The system consists of an electret microphone, amplifier and filter. It makes use of the windows sound card and associated software for data acquisition and analysis. The measurement system is calibrated using a professional sound level meter. Acoustic noise measurements are made on an induction motor drive using the proposed system as per relevant international standards. These measurements are seen to match closely with those of a professional meter.

Experimental Study on Dead-Time Induced Oscillations in a 100-kW Open-Loop Induction Motor Drive

This paper reports instability and oscillations in the stator current under light-load conditions in a practical 100-kW induction motor drive. Dead-time is shown to be a cause for such oscillations. This paper shows experimentally that these oscillations could be mitigated significantly with the help of a simple dead-time compensation scheme.

On-line Estimation of Fundamental and Ripple Components of Line Currents in a Voltage-Source Inverter Operated at Low Switching Frequency

High-power voltage-source inverters (VSI) are often switched at low frequencies due to switching loss constraints. Numerous low-switching-frequency PWM techniques have been reported, which are quite successful in reducing the total harmonic distortion under open-loop conditions at such low operating frequencies. However, the line current still contains low-frequency components (though of reduced amplitudes), which are fed back to the current loop controller during closed-loop operation. Since the harmonic frequencies are quite low and are not much higher than the bandwidth of the current loop, these are amplified by the current controller, causing oscillations and instability. Hence, only the fundamental current should be fed back. Filtering out these harmonics from the measured current (before feeding back) leads to phase shift and attenuation of the fundamental component, while not eliminating the harmonics totally. This paper proposes a method for on-line extraction of the fundamental current in induction motor drives, modulated with low-switching-frequency PWM. The proposed method is validated through simulations on MATLAB/Simulink. Further, the proposed algorithm is implemented on Cyclone FPGA based controller board. Experimental results are presented for an R-L load.

An Improved Dead-Time Compensation Scheme for Voltage Source Inverters Considering the Device Switching Transition Times

Inverter dead-time, which is meant to prevent shoot-through fault, causes harmonic distortion and change in the fundamental voltage in the inverter output. Typical dead-time compensation schemes ensure that the amplitude of the fundamental output current is as desired, and also improve the current waveform quality significantly. However, even with compensation, the motor line current waveform is observed to be distorted close to the current zero-crossings. The IGBT switching transition times being significantly longer at low currents than at high currents is an important reason for this zero-crossover distortion. Hence, this paper proposes an improved dead-time compensation scheme, which makes use of the measured IGBT switching transition times at low currents. Measured line current waveforms in a 2.2 kW induction motor drive with the proposed compensation scheme are compared against those with the conventional dead-time compensation scheme and without dead-time compensation. The experimental results on the motor drive clearly demonstrate the improvement in the line current waveform quality with the proposed method.

Small-Signal Stability Analysis of an Open-loop Induction Motor Drive Including the Effect of Inverter Dead-Time

This paper demonstrates light-load instability in open-loop induction motor drives on account of inverter dead-time. The dynamic equations of an inverter fed induction motor, incorporating the effect of dead-time, are considered. A procedure to derive the small-signal model of the motor, including the effect of inverter dead-time, is presented. Further, stability analysis is carried out on a 100-kW, 415V, 3-phase induction motor considering no-load. For voltage to frequency (i.e. V/f) ratios between 0.5 and 1 pu, the analysis brings out regions of instability on the V-f plane, in the frequency range between 5Hz and 20Hz. Simulation and experimental results show sub-harmonic oscillations in the motor current in this region, confirming instability as predicted by the analysis.

An Advanced Gate Driver for Insulated Gate Bipolar Transistors to Eliminate Dead-time Induced Distortions in Inverter Output

Dead-time is introduced between the gating signals to the top and bottom switches in a voltage source inverter (VSI) leg, to prevent shoot through fault due to the finite turn-off times of IGBTs. The dead-time results in a delay when the incoming device is an IGBT, resulting in error voltage pulses in the inverter output voltage. This paper presents the design, fabrication and testing of an advanced gate driver, which eliminates dead-time and consequent output distortion. Here, the gating pulses are generated such that the incoming IGBT transition is not delayed and shoot-through is also prevented. The various logic units of the driver card and fault tolerance of the driver are verified through extensive tests on different topologies such as chopper, half-bridge and full-bridge inverter, and also at different conditions of load. Experimental results demonstrate the improvement in the load current waveform quality with the proposed circuit, on account of elimination of dead-time.

Analytical evaluation of harmonic distortion factor corresponding to generalised advanced bus-clamping pulse width modulation

A few advanced bus-clamping pulse width modulation (ABCPWM) methods have been proposed recently for a three-phase inverter. With these methods, each phase is clamped, switched at nominal frequency, and switched at twice the nominal frequency in different regions of the fundamental cycle. This study proposes a generalised ABCPWM scheme, encompassing the few ABCPWM schemes that have been proposed and many more ABCPWM schemes that have not been reported yet. Furthermore, analytical closed-form expression is derived for the harmonic distortion factor corresponding to the generalised ABCPWM. This factor is independent of load parameters. The analytical expression derived here brings out the dependence of root-mean-square (RMS) current ripple on modulation index, and can be used to evaluate the RMS current ripple corresponding to any ABCPWM scheme. The analytical closed-form expression is validated experimentally in terms of measured weighted total harmonic distortion (THD) in line voltage (V-WTHD) and measured THD in line current (I-THD) on a 6 kW induction motor drive.

A 5th and 7th order harmonic suppression scheme using capacitive filtering for 2-level VSI fed IM drive

In this paper, a 5th and 7th harmonic suppression technique for a 2-level VSI fed IM drive, by using capacitive filtering is proposed. A capacitor fed 2-level inverter is used on an open-end winding induction motor to suppress all 5th and 7th order harmonics. A PWM scheme that maintains the capacitor voltage, while suppressing the harmonics is also proposed. The proposed scheme is valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter.

Space-Vector-Based Hybrid PWM Technique to Reduce Peak-to-Peak Torque Ripple in Induction Motor Drives

Special switching sequences involving division of active state time are used in space-vector-based generation of pulse width modulation (PWM) waveforms. This paper proposes a hybrid PWM technique which is a combination of the conventional and special switching sequences. The proposed hybrid PWM technique reduces the peak-to-peak torque ripple at high speeds of an induction motor drive. Supporting simulation and experimental results are presented from a closed-loop controlled motor drive.

Low-frequency dc bus ripple cancellation in single phase pulse-width modulation inverters

This study presents a topology for a single-phase pulse-width modulation (PWM) converter which achieves low-frequency ripple reduction in the dc bus even when there are grid frequency variations. A hybrid filter is introduced to absorb the low-frequency current ripple in the dc bus. The control strategy for the proposed filter does not require the measurement of the dc bus ripple current. The design criteria for selecting the filter components are also presented in this study. The effectiveness of the proposed circuit has been tested and validated experimentally. A smaller dc-link capacitor is sufficient to keep the low-frequency bus ripple to an acceptable range in the proposed topology.