Host-Guest interaction between herbicide oxadiargyl and hydroxypropyl-β-cyclodextrin

In the face of a growing human population and increased urbanization, the demand for pesticides will simply rise. Farmers must escalate yields on increasingly fewer farm acres. However, the risks of pesticides, whether real or perceived, may force changes in the way these chemicals are used. Scientists are working toward pest control plans that are environmentally sound, effective, and profitable. In this context the development of new pesticide formulations which may improve application effectiveness, safety, handling, and storage can be pointed out as a solution. As a contribution to the area, the microencapsulation of the herbicide oxadiargyl (OXA) in (2-hydroxypropyl)-β-cyclodextrin (HP-β-CD) was performed. The study was conducted in different aqueous media (ultrapure water and in different pH buffer solutions). In all cases an increment of the oxadiargyl solubility as a function of the HP-β-CD concentration that has been related to the formation of an inclusion complex was verified. UV-Vis and NMR experiments allowed concluding that the stoichiometry of the OXA/HP-β-CD complex formed is 1 : 1. The gathered results can be regarded as an important step for its removal from industrial effluents and/or to increase the stabilizing action, encapsulation, and adsorption in water treatment plants.

Uncertainty assessment approach for composite structures based on global sensitivity indices

The problem of uncertainty propagation in composite laminate structures is studied. An approach based on the optimal design of composite structures to achieve a target reliability level is proposed. Using the Uniform Design Method (UDM), a set of design points is generated over a design domain centred at mean values of random variables, aimed at studying the space variability. The most critical Tsai number, the structural reliability index and the sensitivities are obtained for each UDM design point, using the maximum load obtained from optimal design search. Using the UDM design points as input/output patterns, an Artificial Neural Network (ANN) is developed based on supervised evolutionary learning. Finally, using the developed ANN a Monte Carlo simulation procedure is implemented and the variability of the structural response based on global sensitivity analysis (GSA) is studied. The GSA is based on the first order Sobol indices and relative sensitivities. An appropriate GSA algorithm aiming to obtain Sobol indices is proposed. The most important sources of uncertainty are identified.

A Política de Escola a Tempo Inteiro e a monopolização da educação da criança pela escola

No presente texto problematiza-se a política de Escola a Tempo Inteiro (ETI) a partir de um “modelo” de operacionalização que assenta na tentativa de articulação das “ideias” de igualdade de oportunidades e de eficácia do sistema educativo. Consubstancia-se, assim, num projeto educativo nacional promotor da educação integral da criança, no tempo e no espaço escolares, e da monopolização, pela escola pública, da prestação de serviços educativos provocando o “esvaziamento” e a reconfiguração de outras agências e projetos educativos da comunidade local. As tensões e os desafios subjacentes ao “modelo” de operacionalização da política de ETI jogam-se, em parte, na relação entre a necessidade de assegurar o projeto educativo do Estado e a exigência de abertura a projetos educativos locais e a outros profissionais alicerçada na cooperação entre a escola pública e a comunidade a que pertence, no âmbito da prestação de serviços educativos de qualidade para todos.

Gestão estratégica das organizações : sua aplicabilidade numa instituição financeira : o caso "Grupo Banco Espírito Santo"

Mestrado em Contabilidade e Gestão das Instituições Financeiras

Integrated analysis of climate, soil, topography and vegetative growth in Iberian viticultural regions

The Iberian viticultural regions are convened according to the Denomination of Origin (DO) and present different climates, soils, topography and management practices. All these elements influence the vegetative growth of different varieties throughout the peninsula, and are tied to grape quality and wine type. In the current study, an integrated analysis of climate, soil, topography and vegetative growth was performed for the Iberian DO regions, using state-of-the-art datasets. For climatic assessment, a categorized index, accounting for phenological/thermal development, water availability and grape ripening conditions was computed. Soil textural classes were established to distinguish soil types. Elevation and aspect (orientation) were also taken into account, as the leading topographic elements. A spectral vegetation index was used to assess grapevine vegetative growth and an integrated analysis of all variables was performed. The results showed that the integrated climate-soil-topography influence on vine performance is evident. Most Iberian vineyards are grown in temperate dry climates with loamy soils, presenting low vegetative growth. Vineyards in temperate humid conditions tend to show higher vegetative growth. Conversely, in cooler/warmer climates, lower vigour vineyards prevail and other factors, such as soil type and precipitation acquire more important roles in driving vigour. Vines in prevailing loamy soils are grown over a wide climatic diversity, suggesting that precipitation is the primary factor influencing vigour. The present assessment of terroir characteristics allows direct comparison among wine regions and may have great value to viticulturists, particularly under a changing climate.

A CMOS micro power switched-capacitor DC-DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V-OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm(2) in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm(2), is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m(2). After starting-up, the system requires an irradiance of only 0.18 W/m(2) (18 mu W/cm(2)) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mu W. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 mu W, which is comparable with reported values from circuits operating at similar power levels.

Design and evaluation of multi-band RF energy harvesting circuits and antennas for WSNs

Radio frequency (RF) energy harvesting is an emerging technology that will enable to drive the next generation of wireless sensor networks (WSNs) without the need of using batteries. In this paper, we present RF energy harvesting circuits specifically developed for GSM bands (900/1800) and a wearable dual-band antenna suitable for possible implementation within clothes for body worn applications. Besides, we address the development and experimental characterization of three different prototypes of a five-stage Dickson voltage multiplier (with match impedance circuit) responsible for harvesting the RF energy. Different printed circuit board (PCB) fabrication techniques to produce the prototypes result in different values of conversion efficiency. Therefore, we conclude that if the PCB fabrication is achieved by means of a rigorous control in the photo-positive method and chemical bath procedure applied to the PCB it allows for attaining better values for the conversion efficiency. All three prototypes (1, 2 and 3) can power supply the IRIS sensor node for RF received powers of -4 dBm, -6 dBm and -5 dBm, and conversion efficiencies of 20, 32 and 26%, respectively. © 2014 IEEE.

Efficient Implementation Of A Single-Precision Floating-Point Arithmetic Unit on FPGA

This paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency. © 2014 Technical University of Munich (TUM).

Energy-Aware Routing And Grooming For IP Transport Over WDM MLR Networks

In this work a mixed integer optimization linear programming (MILP) model was applied to mixed line rate (MLR) IP over WDM and IP over OTN over WDM (with and without OTN grooming) networks, with aim to reduce network energy consumption. Energy-aware and energy-aware & short-path routing techniques were used. Simulations were made based on a real network topology as well as on forecasts of traffic matrix based on statistical data from 2005 up to 2017. Energy aware routing optimization model on IPoWDM network, showed the lowest energy consumption along all years, and once compared with energy-aware & short-path routing, has led to an overall reduction in energy consumption up to 29%, expecting to save even more than shortest-path routing. © 2014 IEEE.

Incremental filter and wrapper approaches for feature discretization

Discrete data representations are necessary, or at least convenient, in many machine learning problems. While feature selection (FS) techniques aim at finding relevant subsets of features, the goal of feature discretization (FD) is to find concise (quantized) data representations, adequate for the learning task at hand. In this paper, we propose two incremental methods for FD. The first method belongs to the filter family, in which the quality of the discretization is assessed by a (supervised or unsupervised) relevance criterion. The second method is a wrapper, where discretized features are assessed using a classifier. Both methods can be coupled with any static (unsupervised or supervised) discretization procedure and can be used to perform FS as pre-processing or post-processing stages. The proposed methods attain efficient representations suitable for binary and multi-class problems with different types of data, being competitive with existing methods. Moreover, using well-known FS methods with the features discretized by our techniques leads to better accuracy than with the features discretized by other methods or with the original features. (C) 2013 Elsevier B.V. All rights reserved.

Neighbour list optimization for real LTE radio network

With the increasing complexity of current networks, it became evident the need for Self-Organizing Networks (SON), which aims to automate most of the associated radio planning and optimization tasks. Within SON, this paper aims to optimize the Neighbour Cell List (NCL) for Long Term Evolution (LTE) evolved NodeBs (eNBs). An algorithm composed by three decisions were were developed: distance-based, Radio Frequency (RF) measurement-based and Handover (HO) stats-based. The distance-based decision, proposes a new NCL taking account the eNB location and interference tiers, based in the quadrants method. The last two algorithms consider signal strength measurements and HO statistics, respectively; they also define a ranking to each eNB and neighbour relation addition/removal based on user defined constraints. The algorithms were developed and implemented over an already existent radio network optimization professional tool. Several case studies were produced using real data from a Portuguese LTE mobile operator. © 2014 IEEE.

Perceptually driven video error protection using a distributed source coding approach

In video communication systems, the video signals are typically compressed and sent to the decoder through an error-prone transmission channel that may corrupt the compressed signal, causing the degradation of the final decoded video quality. In this context, it is possible to enhance the error resilience of typical predictive video coding schemes using as inspiration principles and tools from an alternative video coding approach, the so-called Distributed Video Coding (DVC), based on the Distributed Source Coding (DSC) theory. Further improvements in the decoded video quality after error-prone transmission may also be obtained by considering the perceptual relevance of the video content, as distortions occurring in different regions of a picture have a different impact on the user's final experience. In this context, this paper proposes a Perceptually Driven Error Protection (PDEP) video coding solution that enhances the error resilience of a state-of-the-art H.264/AVC predictive video codec using DSC principles and perceptual considerations. To increase the H.264/AVC error resilience performance, the main technical novelties brought by the proposed video coding solution are: (i) design of an improved compressed domain perceptual classification mechanism; (ii) design of an improved transcoding tool for the DSC-based protection mechanism; and (iii) integration of a perceptual classification mechanism in an H.264/AVC compliant codec with a DSC-based error protection mechanism. The performance results obtained show that the proposed PDEP video codec provides a better performing alternative to traditional error protection video coding schemes, notably Forward Error Correction (FEC)-based schemes. (C) 2013 Elsevier B.V. All rights reserved.

ROM-less RNS-to-binary converter moduli {22N − 1, 22N + 1, 2N − 3, 2N + 3}

In this paper, a novel ROM-less RNS-to-binary converter is proposed, using a new balanced moduli set {22n-1, 22n + 1, 2n-3, 2n + 3} for n even. The proposed converter is implemented with a two stage ROM-less approach, which computes the value of X based only in arithmetic operations, without using lookup tables. Experimental results for 24 to 120 bits of Dynamic Range, show that the proposed converter structure allows a balanced system with 20% faster arithmetic channels regarding the related state of the art, while requiring similar area resources. This improvement in the channel's performance is enough to offset the higher conversion costs of the proposed converter. Furthermore, up to 20% better Power-Delay-Product efficiency metric can be achieved for the full RNS architecture using the proposed moduli set. © 2014 IEEE.

Trends Of CPU, GPU and FPGA for high-performance computing

Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM).

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.