Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

Repetitive Solid State Pulse Modulator Based on a DC Voltage Multiplier

A newly developed solid-state repetitive high-voltage (HV) pulse modulator topology created from the mature concept of the d.c. voltage multiplier (VM) is described. The proposed circuit is based in a voltage multiplier type circuit, where a number of d.c. capacitors share a common connection with different voltage rating in each one. Hence, besides the standard VM rectifier and coupling diodes, two solid-state on/off switches are used, in each stage, to switch from the typical charging VM mode to a pulse mode with the d.c. capacitors connected in series with the load. Due to the on/off semiconductor configuration, in half-bridge structures, the maximum voltage blocked by each one is the d.c. capacitor voltage in each stage. A 2 kV prototype is described and the results are compared with PSPICE simulations.

A DC-DC Step-Up mu-Power Converter for Energy Harvesting Applications, Using Maximum Power PointTracking, Based on Fractional Open Circuit Voltage

A DC-DC step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitorvoltage tripler architecture with MOSFET capacitors, which results in an, area approximately eight times smaller than using MiM capacitors for the 0.131mu m CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit is self-clocked, using a phase controller designed specifically to work with an amorphous silicon solar cell, in order to obtain themaximum available power from the cell. This will be done by tracking its maximum power point (MPPT) using the fractional open circuit voltage method. Electrical simulations of the circuit, together with an equivalent electrical model of an amorphous silicon solar cell, show that the circuit can deliver apower of 1132 mu W to the load, corresponding to a maximum efficiency of 66.81%.

Study of vanadium doped ZnO films prepared by dc reactive magnetron sputtering at different substrate temperatures

ZnO films doped with vanadium (ZnO:V) have been prepared by dc reactive magnetron sputtering technique at different substrate temperatures (RT–500 C). The effects of the substrate temperature on ZnO:V films properties have been studied. XRD measurements show that only ZnO polycrystalline structure has been obtained, no V2O5 or VO2 crystal phase can be observed. It has been found that the film prepared at low substrate temperature has a preferred orientation along the (002) direction. As the substrate temperature is increased, the (002) peak intensity decreases. When the substrate temperature reaches the 500 C, the film shows a random orientation. SEM measurements show a clear formation of the nano-grains in the sample surface when the substrate temperature is higher than 400 C. The optical properties of the films have been studied by measuring the specular transmittance. The refractive index has been calculated by fitting the transmittance spectra using OJL model combined with harmonic oscillator.

Effects of sulphurization time on Cu2ZnSnS4 absorbers and thin films solar cells obtained from metallic precursors

We report the results of a study of the sulphurization time effects on Cu2ZnSnS4 absorbers and thin film solar cells prepared from dc-sputtered tackedmetallic precursors. Three different time intervals, 10 min, 30min and 60 min, at maximum sulphurization temperature were considered. The effects of this parameter' change were studied both on the absorber layer properties and on the final solar cell performance. The composition, structure, morphology and thicknesses of the CZTS layers were analyzed. The electrical characterization of the absorber layer was carried out by measuring the transversal electrical resistance of the samples as a function of temperature. This study shows an increase of the conductivity activation energy from 10 meV to 54meV for increasing sulphurization time from 10min to 60min. The solar cells were built with the following structure: SLG/Mo/CZTS/CdS/i-ZnO/ZnO:Al/Ni:Al grid. Several ac response equivalent circuit models were tested to fit impedance measurements. The best results were used to extract the device series and shunt resistances and capacitances. Absorber layer's electronic properties were also determined using the Mott–Schottky method. The results show a decrease of the average acceptor doping density and built-in voltage, from 2.0 1017 cm−3 to 6.5 1015 cm−3 and from 0.71 V to 0.51 V, respectively, with increasing sulphurization time. These results also show an increase of the depletion region width from approximately 90 nm–250 nm.

A study of ternary Cu2SnS3 and Cu3SnS4 thin films prepared by sulfurizing stacked metal precursors

Thin films of Cu2SnS3 and Cu3SnS4 were grown by sulfurization of dc magnetron sputtered Sn–Cu metallic precursors in a S2 atmosphere. Different maximum sulfurization temperatures were tested which allowed the study of the Cu2SnS3 phase changes. For a temperature of 350 ◦C the films were composed of tetragonal (I -42m) Cu2SnS3. The films sulfurized at a maximum temperature of 400 ◦C presented a cubic (F-43m) Cu2SnS3 phase. On increasing the temperature up to 520 ◦C, the Sn content of the layer decreased and orthorhombic (Pmn21) Cu3SnS4 was formed. The phase identification and structural analysis were performed using x-ray diffraction (XRD) and electron backscattered diffraction (EBSD) analysis. Raman scattering analysis was also performed and a comparison with XRD and EBSD data allowed the assignment of peaks at 336 and 351 cm−1 for tetragonal Cu2SnS3, 303 and 355 cm−1 for cubic Cu2SnS3, and 318, 348 and 295 cm−1 for the Cu3SnS4 phase. Compositional analysis was done using energy dispersive spectroscopy and induced coupled plasma analysis. Scanning electron microscopy was used to study the morphology of the layers. Transmittance and reflectance measurements permitted the estimation of absorbance and band gap. These ternary compounds present a high absorbance value close to 104 cm−1. The estimated band gap energy was 1.35 eV for tetragonal (I -42m) Cu2SnS3, 0.96 eV for cubic (F-43m) Cu2SnS3 and 1.60 eV for orthorhombic (Pmn21) Cu3SnS4. A hot point probe was used for the determination of semiconductor conductivity type. The results show that all the samples are p-type semiconductors. A four-point probe was used to obtain the resistivity of these samples. The resistivities for tetragonal Cu2SnS3, cubic Cu2SnS3 and orthorhombic (Pmn21) Cu3SnS4 are 4.59 × 10−2 cm, 1.26 × 10−2 cm, 7.40 × 10−4 cm, respectively.

CuxSnSx+1 (x = 2, 3) thin films grown by sulfurization of metallic precursors deposited by dc magnetron sputtering

We report the results of the growth of Cu-Sn-S ternary chalcogenide compounds by sulfurization of dc magnetron sputtered metallic precursors. Tetragonal Cu2SnS3 forms for a maximum sulfurization temperature of 350 ºC. Cubic Cu2SnS3 is obtained at sulfurization temperatures above 400 ºC. These results are supported by XRD analysis and Raman spectroscopy measurements. The latter analysis shows peaks at 336 cm-1, 351 cm-1 for tetragonal Cu2SnS3, and 303 cm-1, 355 cm-1 for cubic Cu2SnS3. Optical analysis shows that this phase change lowers the band gap from 1.35 eV to 0.98 eV. At higher sulfurization temperatures increased loss of Sn is expected in the sulphide form. As a consequence, higher Cu content ternary compounds like Cu3SnS4 grow. In these conditions, XRD and Raman analysis only detected orthorhombic (Pmn21) phase (petrukite). This compound has Raman peaks at 318 cm-1, 348 cm-1 and 295 cm-1. For a sulfurization temperature of 450 ºC the samples present a multi-phase structure mainly composed by cubic Cu2SnS3 and orthorhombic (Pmn21) Cu3SnS4. For higher temperatures, the samples are single phase and constituted by orthorhombic (Pmn21) Cu3SnS4. Transmittance and reflectance measurements were used to estimate a band gap of 1.60 eV. For comparison we also include the results for Cu2ZnSnS4 obtained using similar growth conditions.

Cu2ZnSnS4 solar cells prepared with sulphurized dc-sputtered stacked metallic precursors

In the present work we report the details of the preparation and characterization results of Cu2ZnSnS4 (CZTS) based solar cells. The CZTS absorber was obtained by sulphurization of dc magnetron sputtered Zn/Sn/Cu precursor layers. The morphology, composition and structure of the absorber layer were studied by scanning electron microscopy, energy dispersive spectroscopy, X-ray diffraction and Raman scattering. The majority carrier type was identified via a hot point probe analysis. The hole density, space charge region width and band gap energy were estimated from the external quantum efficiency measurements. A MoS2 layer that formed during the sulphurization process was also identified and analyzed in this work. The solar cells had the following structure: soda lime glass/Mo/CZTS/CdS/i-ZnO/ZnO:Al/Al grid. The best solar cell showed an opencircuit voltage of 345 mV, a short-circuit current density of 4.42 mA/cm2, a fill factor of 44.29% and an efficiency of 0.68% under illumination in simulated standard test conditions: AM 1.5 and 100 mW/cm2.

A CMOS micro power switched-capacitor DC-DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V-OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm(2) in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm(2), is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m(2). After starting-up, the system requires an irradiance of only 0.18 W/m(2) (18 mu W/cm(2)) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mu W. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 mu W, which is comparable with reported values from circuits operating at similar power levels.

Inverse dynamics based predictive control for unified power flow controllers without DC bus

This paper presents a new predictive digital control method applied to Matrix Converters (MC) operating as Unified Power Flow Controllers (UPFC). This control method, based on the inverse dynamics model equations of the MC operating as UPFC, just needs to compute the optimal control vector once in each control cycle, in contrast to direct dynamics predictive methods that needs 27 vector calculations. The theoretical principles of the inverse dynamics power flow predictive control of the MC based UPFC with input filter are established. The proposed inverse dynamics predictive power control method is tested using Matlab/Simulink Power Systems toolbox and the obtained results show that the designed power controllers guarantees decoupled active and reactive power control, zero error tracking, fast response times and an overall good dynamic and steady-state response.

A Design methodology for integrated inductor-based DC-DC converters

A design methodology for monolithic integration of inductor based DC-DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 mu m CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.

Toroid inductor development for a SIC DC-DC converter up to 150kW, based on finite element method

Dissertação para a obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Energia

A PV panel simulator based on a two quadrant DC/DC power converter with a sliding mode controller

The use of a solar photovoltaic (PV) panel simulator can be a valued tool for the design and evaluation of the several components of a photovoltaic system. This simulator is based on power electronic converter controlled in such a way that will behave as a PV panel. Thus, in this paper a PV panel simulator based on a two quadrant DC/DC power converter is proposed. This topology will allow to achieve fast responses, like suddenly changes in the irradiation and temperature. To control the power converter it will be used a fast and robust sliding mode controller. Therefore, with the proposed system I-V curve simulation of a PV panel is obtained. Experimental results from a laboratory prototype are presented in order to confirm the theoretical operation.

Conversor DC-DC com busca de ponto de potência máxima (MPPT) para painéis solares

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Simulation of a-Si PV system linked to the grid by DC boost and three-level inverter under cloud scope

This paper is about a PV system linked to the electric grid through power converters under cloud scope. The PV system is modeled by the five parameters equivalent circuit and a MPPT procedure is integrated into the modeling. The modeling for the converters models the association of a DC-DC boost with a three-level inverter. PI controllers are used with PWM by sliding mode control associated with space vector modulation controlling the booster and the inverter. A case study addresses a simulation to assess the performance of a PV system linked to the electric grid. Conclusions regarding the integration of the PV system into the electric grid are presented. © IFIP International Federation for Information Processing 2015.