IEEE 1451-based multi-interface module (I2M) for industrial processes automation

This paper describes the implementation of a multi-interface module (I2M) for automation of industrial processes, based on the IEEE1451 standard. Process automation with I2M can communicate through either wires or using wireless communication, without any hardware or software changes. We used FPGA resources to implement the I2M functions FPGA, with a NIOS II processor and ZigBee communication system (IEEE802.15), as well as RS232 serial standard. Part of the project was done in the SOPC Builder environment, which gave the designer flexibility and speed to implement the NIOS II-based microprocessor system. To test the I2M implementation, a didactic Industrial Hydraulic Module (MHI-01) was used to simulate two industrial processes to be controlled by the system proposed.

Teaching real-time with a scheduler simulator

In this paper we describe a scheduler simulator for real-time tasks, RTsim, that can be used as a tool to teach real-time scheduling algorithms. It simulates a variety of preprogrammed scheduling policies for single and multi-processor systems and simple algorithm variants introduced by its user. Using RTsim students can conduct experiments that will allow them to understand the effects of each policy given different load conditions and learn which policy is better for different workloads. We show how to use RTsim as a learning tool and the results achieved with its application on the Real-Time Systems course taught at the B.Sc. on Computer Science at Paulista State University - Unesp - at Rio Preto.

Common architecture for discrete wavelet transform analysis and synthesis with sequential and constant processing elements

This paper adresses the problem on processing biological data such as cardiac beats, audio and ultrasonic range, calculating wavelet coefficients in real time, with processor clock running at frequency of present ASIC's and FPGA. The Paralell Filter Architecture for DWT has been improved, calculating wavelet coefficients in real time with hardware reduced to 60%. The new architecture, which also processes IDWT, is implemented with the Radix-2 or the Booth-Wallace Constant multipliers. Including series memory register banks, one integrated circuit Signal Analyzer, ultrasonic range, is presented.

Dynamic and isometric protocols of knee extension: Effect of fatigue on the EMG signal

The objective of this study was to analyze the electromyographic (EMG) signal behavior of rectus femoris (RF), vastus medialis (VM), vastus lateralis (VL) and biceps femoris (caput longum) (BFCL) from nine women during fatiguing dynamic and isometric knee extensions tests and to determine their EMGFT (Electromyographic Fatigue Threshold). Surface electrodes, biological signal acquisition module, analogical-digital converter board and specific software were used. The RMS (Root Mean Square) values obtained from concentric phase (80 to 30 degrees) of the dynamic knee extension andfrom isometric contraction were correlated with time on each load by linear regression analysis. The respective slopes were correlated with the correspondent load to determine the EMGFT. Force (Kgf) and median frequency - MF (Hz) obtained during MIVC (Maximal Isometric Voluntary Contraction) performed before and after the fatiguing tests were calculated in Matlab environment. The results demonstrated that the endurance time decreases with higher loads the EMG amplitude increase with time and was greater at higher loads, between muscles in dynamic exercise the RF and VL showed higher slopes, and in isometric exercise the VL showed the same behavior The EMGFT values were similar in both exercises; the force values predominantly decreased after fatiguing tests; however the MF only decreased after some loads. The protocols proposed allowed standardizing protocols at least to induce the fatigue process and to determine the EMGFT as an endurance indicative, which may be used to evaluate the effectiveness of rehabilitative or training interventions indicated to reduce muscle weakness and fatigue.

GDP 4.0 transfer to SGP 3.0 for SCIAMACHY no2 column processing: Verification with SDOAS / GDOAS prototype algorithms and delta-validation with NDACC / UV-visible network data

Until mid 2006, SCIAMACHY data processors for the operational retrieval of nitrogen dioxide (NO2) column data were based on the historical version 2 of the GOME Data Processor (GDP). On top of known problems inherent to GDP 2, ground-based validations of SCIAMACHY NO2 data revealed issues specific to SCIAMACHY, like a large cloud-dependent offset occurring at Northern latitudes. In 2006, the GDOAS prototype algorithm of the improved GDP version 4 was transferred to the off-line SCIAMACHY Ground Processor (SGP) version 3.0. In parallel, the calibration of SCIAMACHY radiometric data was upgraded. Before operational switch-on of SGP 3.0 and public release of upgraded SCIAMACHY NO2 data, we have investigated the accuracy of the algorithm transfer: (a) by checking the consistency of SGP 3.0 with prototype algorithms; and (b) by comparing SGP 3.0 NO2 data with ground-based observations reported by the WMO/GAW NDACC network of UV-visible DOAS/SAOZ spectrometers. This delta-validation study concludes that SGP 3.0 is a significant improvement with respect to the previous processor IPF 5.04. For three particular SCIAMACHY states, the study reveals unexplained features in the slant columns and air mass factors, although the quantitative impact on SGP 3.0 vertical columns is not significant.

Discrete wavelet transform signal analyzer

This paper addresses the problem of processing biological data, such as cardiac beats in the audio and ultrasonic range, and on calculating wavelet coefficients in real time, with the processor clock running at a frequency of present application-specified integrated circuits and field programmable gate array. The parallel filter architecture for discrete wavelet transform (DWT) has been improved, calculating the wavelet coefficients in real time with hardware reduced up to 60%. The new architecture, which also processes inverse DWT, is implemented with the Radix-2 or the Booth-Wallace constant multipliers. One integrated circuit signal analyzer in the ultrasonic range, including series memory register banks, is presented. © 2007 IEEE.

Back to school with tablets embedded in digital desks

A digital-desk pilot program, named One Laptop Per Child (OPLC), in Brazil uses a unique display design to provide an interactive interface developed to enhance education and minimize ergonomic concerns. The one-to-one computer strategy as proposed by Nicholas Negroponte is a way of circumventing the tragedy of the locked computer lab because it gives children full access to computers anytime. The OLPC program has focused on a solution that minimizes power consumption, which also limits the display's maximum size and processor performance because the LCD backlights are responsible for a significant part of the power consumption in laptops. The government has also developed a new type of low-cost tablet that is based on a resistive principle. High transparencies can be obtained in the 90% range in the tablet, while robustness is guaranteed by the outstanding tribological characteristics of Sn02 on glass.

Methodology proposal for acquisition of biotelemetric data in a real time

This work presents a methodological proposal for acquisition of biometric data through telemetry basing its development on a research-action and a case study. Nowadays, the qualified professionals of physical evaluation have to use specific devices to obtain biometric signals and data. These devices in the most of the time are high cost and difficult to use and handling. Therefore, the methodological proposal was elaborate in order to develop, conceptually, a bio telemetric device which could acquire the desirable biometric signals: oxymetry, biometrics, corporal temperature and pedometry which are essential for the area of physical evaluation. It was researched the existent biometrics sensors, the possible ways for the remote transmission of signals and the computer systems available so that the acquisition of data could be possible. This methodological proposal of remote acquisition of biometrical signals is structured in four modules: Acquisitor of biometrics data; Converser and transmitter of biometric signals; Receiver and Processor of biometrics signals and Generator of Interpretative Graphs. The modules aim the obtention of interpretative graphics of human biometric signals. In order to validate this proposal a functional prototype was developed and it is presented in the development of this work.

Conversor CA-CA de elevado fator de potência para aplicações com geradores de Ímã permanente

This paper proposes and describes a high power factor AC-AC converter for naval applications using Permanent Magnet Generator (PMG). The three-phase output voltages of the PMG vary from 260 Vrms (220 Hz) to 380 Vrms (360 Hz), depending on load conditions. The proposed converter consists of a Y-/ΔY power transformer, which provides electrical isolation between the PMG and remaining stages, and a twelve-pulse uncontrolled rectifier stage directly connected to a single-phase inverter stage, without the use of an intermediary DC-DC topology. This proposal results in more simplicity for the overall circuitry, assuring robustness, reliability and reduced costs. Furthermore, the multipulse rectifier stage is capable to provide high power factor and low total harmonic distortion for the input currents of the converter. The single-phase inverter stage was designed to operate with wide range of DC bus voltage, maintaining 120 Vrms, 60 Hz output. The control philosophy, implemented in a digital signal processor (DSP) which also contains protection routines, alows series connections between two identical converters, achieving 240 Vrms, 60 Hz total output voltage. Measured total harmonic distortion for the AC output voltage is lower than 2% and the input power factor is 0.93 at 3.6kW nominal load. © 2010 IEEE.

Dependência estrutural da capacidade de rotação plástic em vigas de concreto armado

Summary In this work the structural dependence of plastic rotation capacity in RC beams is evaluated using the Finite Element Method. The objective is to achieve a better understanding of the non-linear behavior of reinforced concrete members and perform extensive parameter studies, using a rational model developed by Bigaj [1] to analyze the phenomenon of plastic rotation capacity in reinforced concrete members. It is assumed that only bending failure is relevant due to sufficient member resistance against shear and torsion. The paper begins with the physical and theoretical background of the phenomenon of plastic hinge development in RC structures. Special emphasis is laid on the issue of structural dependence of deformation capacity of plastic hinges in RC members. Member size dependence and influence of properties of construction materials were emphasized as well. The essential components of the Bigajs model for calculating the plastic rotation capacity are discussed. The behaviour of the plastic hinge is analysed taking into account the strain localisation in the damage zones of the hinge region. The Fictitious Crack Model (FCM) and the Compressive Damage Zone Model (CDZ) are adopted in a Fracture Mechanics approach to model the behaviour of concrete in tension and compression, respectively. The approach is implemented in FEMOOP, a FEM in-house solver under development, and applied to evaluate ductility in 2D beams. The models were generated with GiD, a pre-processor and post-processor developed by CIMNE, and analyzed with the capabilities implemented in FEMOOP. © Universitat Politècnica de Catalunya, Barcelona, España 2010.

LUTS: A lightweight user-level transaction scheduler

Software Transactional Memory (STM) systems have poor performance under high contention scenarios. Since many transactions compete for the same data, most of them are aborted, wasting processor runtime. Contention management policies are typically used to avoid that, but they are passive approaches as they wait for an abort to happen so they can take action. More proactive approaches have emerged, trying to predict when a transaction is likely to abort so its execution can be delayed. Such techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction should run. In this paper we propose LUTS, a Lightweight User-Level Transaction Scheduler, which is based on an execution context record mechanism. Unlike other techniques, LUTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. Moreover, it avoids most of the issues caused by pseudo parallelism, as it only launches as many system-level threads as the number of available processor cores. We discuss LUTS design and present three conflict-avoidance heuristics built around LUTS scheduling capabilities. Experimental results, conducted with STMBench7 and STAMP benchmark suites, show LUTS efficiency when running high contention applications and how conflict-avoidance heuristics can improve STM performance even more. In fact, our transaction scheduling techniques are capable of improving program performance even in overloaded scenarios. © 2011 Springer-Verlag.

HW/SW for an intelligent transducer network based on IEEE 1451 standard

This work describes a hardware/software co-design system development, named IEEE 1451 platform, to be used in process automation. This platform intends to make easier the implementation of IEEE standards 1451.0, 1451.1, 1451.2 and 1451.5. The hardware was built using NIOS II processor resources on Alteras Cyclone II FPGA. The software was done using Java technology and C/C++ for the processors programming. This HW/SW system implements the IEEE 1451 based on a control module and supervisory software for industrial automation. © 2011 Elsevier B.V.

NCAP embedded using structured programming

This paper presents a network node embedded based on IEEE 1451 standard developed using structured programming to access the transducers in the WTIM. The NCAP was developed using Nios II processor and uClinux, a embedded operating system developed to features restricted hardware. Both hardware and software have dynamics features and they can be configured based in the application features. Based in this features, the NCAP was developed using the minimum components of hardware and software to that being implemented in remote environment like central point of data request. Many NCAP works are implemented with an object oriented structure. This is different from the surrounding implementations. In this project the NCAP was developed using structured programming. The tests of the NCAP were made using a ZigBee interface between NCAP and WTIM and the system demonstrated in areas of difficult access for long period of time due to need for low power consumption. © 2012 IEEE.

Energy-performance tradeoffs in software transactional memory

Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of TM (STM) have been extensively analyzed in terms of runtime performance, little attention has been paid to an equally important constraint faced by nearly all computer systems: energy consumption. In this work we conduct a comprehensive study of energy and runtime tradeoff sin software transactional memory systems. We characterize the behavior of three state-of-the-art lock-based STM algorithms, along with three different conflict resolution schemes. As a result of this characterization, we propose a DVFS-based technique that can be integrated into the resolution policies so as to improve the energy-delay product (EDP). Experimental results show that our DVFS-enhanced policies are indeed beneficial for applications with high contention levels. Improvements of up to 59% in EDP can be observed in this scenario, with an average EDP reduction of 16% across the STAMP workloads. © 2012 IEEE.

Transaction scheduling using dynamic conflict avoidance

Software transaction memory (STM) systems have been used as an approach to improve performance, by allowing the concurrent execution of atomic blocks. However, under high-contention workloads, STM-based systems can considerably degrade performance, as transaction conflict rate increases. Contention management policies have been used as a way to select which transaction to abort when a conflict occurs. In general, contention managers are not capable of avoiding conflicts, as they can only select which transaction to abort and the moment it should restart. Since contention managers act only after a conflict is detected, it becomes harder to effectively increase transaction throughput. More proactive approaches have emerged, aiming at predicting when a transaction is likely to abort, postponing its execution. Nevertheless, most of the proposed proactive techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction to run. This article proposes LUTS, a lightweight user-level transaction scheduler. Unlike other techniques, LUTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. We discuss LUTS design and propose a dynamic conflict-avoidance heuristic built around its scheduling capabilities. Experimental results, conducted with the STAMP and STMBench7 benchmark suites, running on TinySTM and SwissTM, show how our conflict-avoidance heuristic can effectively improve STM performance on high contention applications. © 2012 Springer Science+Business Media, LLC.