Electromagnetic wave diffraction from an infinite array of complex-shaped microstrip reflectors

A numerical-analytical method is developed for solving surface integral equations (IEs) describing electromagnetic wave diffraction from arrays of complex-shaped planar reflectors. Solutions to these equations are regularized via analytical transformation of the separated singular part of the matrix kernel. Basis functions satisfying the metal-edge condition are determined on the entire surface of the complex region. The amplitude and phase responses of arrays consisting of polygonal reflectors are numerically investigated.

QCA Systolic array design

Quantum-dot Cellular Automata (QCA) technology is a promising potential alternative to CMOS technology. To explore the characteristics of QCA and suitable design methodologies, digital circuit design approaches have been investigated. Due to the inherent wire delay in QCA, pipelined architectures appear to be a particularly suitable design technique. Also, because of the pipeline nature of QCA technology, it is not suitable for complicated control system design. Systolic arrays take advantage of pipelining, parallelism and simple local control. Therefore, an investigation into these architectures in QCA technology is provided in this paper. Two case studies, (a matrix multiplier and a Galois Field multiplier) are designed and analyzed based on both multilayer and coplanar crossings. The performance of these two types of interconnections are compared and it is found that even though coplanar crossings are currently more practical, they tend to occupy a larger design area and incur slightly more delay. A general semi-conductor QCA systolic array design methodology is also proposed. It is found that by applying a systolic array structure in QCA design, significant benefits can be achieved particularly with large systolic arrays, even more so than when applied in CMOS-based technology.

Rotman lens based-retrodirective array

A new type of broadband retrodirective array, which has been constructed using a microstrip Rotman lens, is presented. Automatic tracking of targets is obtained by exploiting the conjugate phase response of the beamforming network which is exhibited when the input ports are terminated with either open or short circuits. In addition, the true time-delay property of the Rotman lens gives broadband operation of the self-tracking array when used in conjunction with Vivaldi antennas. The simulated and measured bistatic and monostatic radar cross-section (RCS) patterns of a structure consisting of 13 beamports and 12 array ports are presented at frequencies in the range 8-12 GHz. Significantly enhanced RCS within the scan coverage ±40° is demonstrated by comparing the retrodirective behavior of a 12-element Vivaldi array terminated with and without the Rotman lens. © 2006 IEEE.

Generation of a train of ultrashort pulses from a compact birefringent crystal array

A linear array of n calcite crystals is shown to allow the generation of a high contrast (> 10: 1) train of 2(n) high energy (> 100 mu J) pulses from a single ultrafast laser pulse. Advantage is taken of the pulse-splitting properties of a single birefringent crystal, where an incident laser pulse can be split into two pulses with orthogonal polarizations and equal intensity, separated temporally in proportion to the thickness of the crystal traversed and the difference in refractive indices of the two optic axes. In the work presented here an array of seven calcite crystals of sequentially doubled thickness is used to produce a train of 128 pulses, each of femtosecond duration. Readily versatile properties such as the number of pulses in the train and variable mark-space ratio are realized from such a setup. (c) 2007 Optical Society of America

YIELD ENHANCEMENT OF BIT LEVEL SYSTOLIC ARRAY CHIPS USING FAULT TOLERANT TECHNIQUES.

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics authors demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.