A Shine of Truth in the "universal delusional context of reification" (Theodor W. Adorno)

“A Shine of Truth in the ‘universal delusional context of reification’ (Theodor W. Adorno)” comprend sept chapitres, un prologue et un épilogue. Chaque partie se construit à deux niveaux : (1) à partir des liens qui se tissent entre les phrases contiguës ; et (2) à partir des liens qui se tissent entre les phrases non contiguës. Les incipit des paragraphes forment l’argument principal de la thèse. Le sujet de la thèse, Schein (apparence, illusion, clarté) est abordé de manière non formaliste, c’est à dire, de manière que la forme donne d’elle-même une idée de la chose : illusion comme contradiction imposée. Bien que le sujet de la thèse soit l’illusion, son but est la vérité. Le Chapitre I présente une dialectique de perspectives (celles de Marx, de Lukács, de Hegel, de Horkheimer et d'Adorno) pour arriver à un critère de vérité, compte tenu du contexte d’aveuglement universel de la réification ; c’est la détermination de la dissolution de l’apparence. Le Chapitre II présente le concept d’apparence esthétique—une apparence réversible qui s’oppose à l’apparence sociale générée par l’industrie de la culture. Le Chapitre III cherche à savoir si la vérité en philosophie et la vérité en art sont deux genres distincts de vérités. Le Chapitre IV détermine si l’appel à la vérité comme immédiateté de l’expression, fait par le mouvement expressionniste du 20e siècle, est nouveau, jugé à l’aune d’un important antécédent à l’expressionisme musical : « Der Dichter spricht » de Robert Schumann. Le Chapitre V se penche sur la question à savoir si le montage inorganique est plus avancé que l’expressionisme. Le Chapitre VI reprend là où Peter Bürger clôt son essai Theorie de l’avant-garde : ce chapitre cherche à savoir à quel point l’oeuvre d’art après le Dada et le Surréalisme correspond au modèle hégélien de la « prose ». Le Chapitre VII soutient que Dichterliebe, op. 48, (1840), est une oeuvre d’art vraie. Trois conclusions résultent de cette analyse musicale détaillée : (1) en exploitant, dans certains passages, une ambigüité dans les règles de l’harmonie qui fait en sorte tous les douze tons sont admis dans l’harmonie, l’Opus 48 anticipe sur Schoenberg—tout en restant une musique tonale ; (2) l’Opus 48, no 1 cache une tonalité secrète : à l'oeil, sa tonalité est soit la majeur, soit fa-dièse mineur, mais une nouvelle analyse dans la napolitaine de do-dièse majeur est proposée ici ; (3) une modulation passagère à la napolitaine dans l’Opus 48, no 12 contient l’autre « moitié » de la cadence interrompue à la fin de l’Opus 48, no 1. Considérés à la lumière de la société fausse, l’Allemagne des années 1930, ces trois aspects anti-organiques témoignent d’une conscience avancée. La seule praxis de vie qu’apporte l’art, selon Adorno, est la remémoration. Mais l’effet social ultime de garder la souffrance vécue en souvenir est non négligeable : l’émancipation universelle.

Lectura feminista de las Comedias bárbaras de Ramón del Valle-Inclán : Lilith y las mujeres en la decadencia del patriarcado

Ce mémoire traite des Comedias bárbaras (« Águila de blasón », « Romance de lobos » et « Cara de plata », 1907-1908-1922) de Ramón María del Valle-Inclán (Espagne, 1866-1936), et en fait une interprétation novatrice, différente de la réception dominante. Inspiré par les études sur le genre, ce travail revisite la trilogie en mettant l’emphase sur la perspective des personnages féminins qui contraste avec la figure prépondérante du mythe de Lilith (ou l’idée de la responsabilité légendaire du péché qui repose sur la femme, démoniaque). L’analyse des relations de genre présentes dans l’œuvre apparaît primordiale étant donné que le personnage de Don Juan Manuel Montenegro est aussi une version de la légende de don Juan. De plus, en recensant les différents discours sur celui-ci ainsi que les éléments grotesques des récits, on perçoit dans le traitement du personnage principal une critique qui va au-delà de la société de l’époque, et qui révèle une critique universelle des logiques mêmes qui régissent le système patriarcal, en passant par une réflexion sur la légitimité du pouvoir. Toutes ces considérations permettent d’apprécier l’ensemble de la trilogie dans les aspects qui la rapproche de l’esthétique postérieure de l’esperpento. Cette interprétation contemporaine entre en dialogue avec les aspects centraux des différents débats qu’auront suscités ces œuvres depuis leur parution (représentabilité, genre littéraire, unité ou non de la trilogie, classification) et revitalise sa réception dans le XXIe siècle, révélant la fascinante actualité du théâtre de l’auteur.

On Implementing Joins, Aggregates and Universal Quantifier in Temporal Databases using SQL Standards

A feasible way of implementing a temporal database is by mapping temporal data model onto a conventional data model followed by a commercial database management system. Even though extensions were proposed to standard SQL for supporting temporal databases, such proposals have not yet come across standardization processes. This paper attempts to implement database operators such as aggregates and universal quantifier for temporal databases, implemented on top of relational database systems, using currently available SQL standards.

Universal behaviour in a ``modulated'' logistic map

We study the period-doubling bifurcations to chaos in a logistic map with a nonlinearly modulated parameter and show that the bifurcation structure is modified significantly. Using the renormalisation method due to Derrida et al. we establish the universal behaviour of the system at the onset of chaos.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

Studies on the universal parameters and onset of chaos in dissipative systems

It has become clear over the last few years that many deterministic dynamical systems described by simple but nonlinear equations with only a few variables can behave in an irregular or random fashion. This phenomenon, commonly called deterministic chaos, is essentially due to the fact that we cannot deal with infinitely precise numbers. In these systems trajectories emerging from nearby initial conditions diverge exponentially as time evolves)and therefore)any small error in the initial measurement spreads with time considerably, leading to unpredictable and chaotic behaviour The thesis work is mainly centered on the asymptotic behaviour of nonlinear and nonintegrable dissipative dynamical systems. It is found that completely deterministic nonlinear differential equations describing such systems can exhibit random or chaotic behaviour. Theoretical studies on this chaotic behaviour can enhance our understanding of various phenomena such as turbulence, nonlinear electronic circuits, erratic behaviour of heart and brain, fundamental molecular reactions involving DNA, meteorological phenomena, fluctuations in the cost of materials and so on. Chaos is studied mainly under two different approaches - the nature of the onset of chaos and the statistical description of the chaotic state.

Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Fixed Point Decimal Multiplication Using RPS Algorithm

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.

Automated synthesis of delay-reduced Reed-Muller universal logic module networks

This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables.