975 resultados para CMOS synchronous circuits


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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

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In this article, it is represented by state variables phase a transmission line which parameters are considered frequency independently and frequency dependent. Based on previous analyses, it is used the reasonable number of p circuits and the number of blocks composed by parallel resistor and inductor for reduction of numerical oscillations. It is analyzed the influence of the increase of the RL parallel blocks in the obtained results. The RL parallel blocks are used for inclusion of the frequency influence in the transmission line longitudinal parameter. It is a simple model that is been used by undergraduate students for simulation of traveling wave phenomena in transmission lines. Considering the model without frequency influence, it is included a representation of the corona effect. Some simulations are carried considering the corona effect and they are compared to the results without this phenomenon.

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In this article, it is represented by state variables phase a transmission line which parameters are considered frequency independently and frequency dependent. It is analyzed what is the reasonable number of pi circuits and the number of blocks composed by parallel resistor and inductor in parallel for reduction of numerical oscillations. It is simulated the numerical routine with and without the effect of frequency in the longitudinal parameters. Initially, it is used state variables and pi circuits representing the transmission line composing a linear system which is solved by numerical routines based on the trapezoidal rule. The effect of frequency on the line is synthesized by resistors and inductors in parallel and this representation is analyzed in details. It is described transmission lines and the frequency influence in these lines through the state variables.

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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

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This work shows a computational methodology for the determination of synchronous machines parameters using load rejection test data. The quadrature axis parameters are obtained with a rejection under an arbitrary reference, reducing the present difficulties.

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Trade-off between settling time and micropower consumption in MOS regulated cascode current sources as building parts in high-accuracy, current-switching D/A converters is analyzed. The regulation-loop frequency characteristic is obtained and difficulties to impose a dominant-pole condition to the resulting 2nd-order system are discussed. Raising pole frequencies while meeting consumption requirements is basically limited by parasitic capacitances. An alternative is found by imposing a twin-pole system in which design constraints are somewhat relaxed and settling slightly faster. Relationships between pole frequencies, transistor geometry and bias are established. Simulated waveforms obtained with PSpice of designed circuits following a voltage perturbation suggest a good agreement with theory. The proposed approach applied to the design of a micropower current-mode D/A converter improves its simulated settling performance.

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This work presents an algorithm for the security control of electric power systems using control actions like generation reallocation, determined by sensitivity analysis (linearized model) and optimization by neural networks. The model is developed taking into account the dynamic network aspects. The preventive control methodology is developed by means of sensitivity analysis of the security margin related with the mechanical power of the system synchronous machines. The reallocation power in each machine is determined using neural networks. The neural network used in this work is of Hopfield type. These networks are dedicated electric circuits which simulate the constraint set and the objective function of an optimization problem. The advantage of using these networks is the higher speed in getting the solutions when compared to conventional optimization algorithms due to the great convergence rate of the process and the facility of the method parallelization. Then, the objectives are: formulate and investigate these networks implementations in determining. The generation reallocation in digital computers. Aiming to illustrate the proposed methodology an application considering a multi-machine system is presented.

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A model for preventive control in electrical systems is presented, taking into account the dynamic aspects of the network. Among these aspects, the effects provoked by perturbations which cause oscillations in synchronous machine angles (transient stability), such as electric equipment outages and short circuits, are presented. The energy function is used to measure the stability of the system using a procedure defined as the security margin. The control actions employed are load shedding and generation reallocation. An application of the methodology to a system located in southern Brazil, which is composed of 10 synchronous machines, 45 busses, and 72 transmission lines. The results confirm the theoretical studies.

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A CMOS audio-equalizer based on a parallel-array of 2nd-order bandpass-sections is presented and realized with triode transconductors. It has a programmable 12db-boost/cut on each of its three decade-bands, easily achieved through the linear dependence of gm on VDS. In accordance with a 0.8μm n-well double-metal fabrication process, a range of simulations supports theoretical analysis and circuit performance at different boost/cut scenarios. For VDD=3.3V, fullboosting stand-by prover consumption is 1.05mW. THD=-42.61dB@1Vpp and may be improved by balanced structures. Thermal- and I/f-noise spectral densities are 3.2μV/Hz12 and 18.2μV/Hz12@20Hz, respectively, for a dynamic range of 52.3dB@1Vpp. The equalizer effective area is 2.4mm2. The drawback of the existing transmission-zero due to the feedthrough-capacitance of a triode input-device is also addressed. The proposed topology can be extended to the design of more complex graphic-equalizers and hearing-aids.

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A low-voltage, low-power four-quadrant analog multiplier with optimized current-efficiency is presented. Its core corresponds to a pseudodifferential cascode, gain-boosting triode-transconductor. According to a low-voltage 1.2μm CMOS n-well process, operand differential-amplitudes are 1.0Vpp and 0.32Vpp for a 1.3V-supply. Common-mode voltages are properly chosen to maximize current-efficiency to 58%. Total quiescent dissipation is 260μW. A range of PSPICE simulation supports theoretical analysis. Excellent linearity is observed on dc characteristic. Assuming a ±0.5% mismatch on (W/L) and VTH THD at full-scale is 0.93% and 1.42%, for output frequencies of 1MHz and 10MHz, respectively.

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This work shows a computational methodology for the determination of synchronous machines parameters using load rejection test data. By machine modeling one can obtain the quadrature parameters through a load rejection under an arbitrary reference, reducing the present difficulties. The proposed method is applied to a real machine.

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A CMOS low-voltage, wide-band continuous-time current amplifier is presented. Based on an open-loop topology, the circuit is composed by transresistance and transconductance stages built around triode-operating transistors. In addition to an extended dynamic range, the amplifier gain can be programmed within good accuracy by the rapport between the aspect-ratio of such transistors and tuning biases Vxand Vy. A balanced current-amplifier according to a single I. IV-supply and a 0.35μm fabrication process is designed. Simulated results from PSPiCE and Bsm3v3 models indicate a programmable gain within the range 20-34dB and a minimum break-frequency of IMHz @CL=IpF. For a 200 μApp-level, THD is 0.8% and 0.9% at IKHz and 100KHz, respectively. Input noise is 405pA√Hz @20dB-gain, which gives a SNR of 66dB @1MHz-bandwidth. Maximum quiescent power consumption is 56μ W. © 2002 IEEE.

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An active leakage-injection scheme (ALIS) for low-voltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a common-drain MOSFET, a current matching the respective bit-line leakage is injected onto the line during precharge and sensing, preventing the respective capacitances from erroneous discharges. The technique is able to handle leakages up to hundreds of μA at high operating temperatures. Since no additional timing is required, read-out operations are performed at no speed penalty. A simplified 256×1bit array was designed in accordance with a 0.35 CMOS process and 1.2V-supply. A range of PSPICE simulation attests the efficacy of ALIS. With an extra power consumption of 242 μW, a 200 μA-leakage @125°C, corresponding to 13.6 times the cell current, is compensated.

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In this work, the planning of secondary distribution circuits is approached as a mixed integer nonlinear programming problem (MINLP). In order to solve this problem, a dedicated evolutionary algorithm (EA) is proposed. This algorithm uses a codification scheme, genetic operators, and control parameters, projected and managed to consider the specific characteristics of the secondary network planning. The codification scheme maps the possible solutions that satisfy the requirements in order to obtain an effective and low-cost projected system-the conductors' adequate dimensioning, load balancing among phases, and the transformer placed at the center of the secondary system loads. An effective algorithm for three-phase power flow is used as an auxiliary methodology of the EA for the calculation of the fitness function proposed for solutions of each topology. Results for two secondary distribution circuits are presented, whereas one presents radial topology and the other a weakly meshed topology. © 2005 IEEE.

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The objective of this paper is to show an alternative methodology to estimate per unit length parameters of a line segment of a transmission line. With this methodology the line segment parameters can be obtained starting from the phase currents and voltages in receiving and sending end of the line segment. If the line segment is represented as being one or more π circuits whose frequency dependent parameters are considered lumped, its impedance and admittance can be easily expressed as functions of the currents and voltages at the sending and receiving end. Because we are supposing that voltages and currents at the sending and receiving end of the line segment (in frequency domain) are known, it is possible to obtains its impedance and admittance and consequently its per unit length longitudinal and transversal parameters. The procedure will be applied to estimate the longitudinal and transversal parameters of a small segment of a single-phase line that is already built. © 2006 IEEE.