Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios

The increasingly request for processing power during last years has pushed integrated circuit industry to look for ways of providing even more processing power with less heat dissipation, power consumption, and chip area. This goal has been achieved increasing the circuit clock, but since there are physical limits of this approach a new solution emerged as the multiprocessor system on chip (MPSoC). This approach demands new tools and basic software infrastructure to take advantage of the inherent parallelism of these architectures. The oil exploration industry has one of its firsts activities the project decision on exploring oil fields, those decisions are aided by reservoir simulations demanding high processing power, the MPSoC may offer greater performance if its parallelism can be well used. This work presents a proposal of a micro-kernel operating system and auxiliary libraries aimed to the STORM MPSoC platform analyzing its influence on the problem of reservoir simulation

Projeto e implementação em FPGA de um processador com conjunto de instrução reconfigurável utilizando VHDL

The Reconfigurable Computing is an intermediate solution at the resolution of complex problems, making possible to combine the speed of the hardware with the flexibility of the software. An reconfigurable architecture possess some goals, among these the increase of performance. The use of reconfigurable architectures to increase the performance of systems is a well known technology, specially because of the possibility of implementing certain slow algorithms in the current processors directly in hardware. Amongst the various segments that use reconfigurable architectures the reconfigurable processors deserve a special mention. These processors combine the functions of a microprocessor with a reconfigurable logic and can be adapted after the development process. Reconfigurable Instruction Set Processors (RISP) are a subgroup of the reconfigurable processors, that have as goal the reconfiguration of the instruction set of the processor, involving issues such formats, operands and operations of the instructions. This work possess as main objective the development of a RISP processor, combining the techniques of configuration of the set of executed instructions of the processor during the development, and reconfiguration of itself in execution time. The project and implementation in VHDL of this RISP processor has as intention to prove the applicability and the efficiency of two concepts: to use more than one set of fixed instructions, with only one set active in a given time, and the possibility to create and combine new instructions, in a way that the processor pass to recognize and use them in real time as if these existed in the fixed set of instruction. The creation and combination of instructions is made through a reconfiguration unit, incorporated to the processor. This unit allows the user to send custom instructions to the processor, so that later he can use them as if they were fixed instructions of the processor. In this work can also be found simulations of applications involving fixed and custom instructions and results of the comparisons between these applications in relation to the consumption of power and the time of execution, which confirm the attainment of the goals for which the processor was developed

Ultrasound effects on invertase from Aspergillus niger

Ultrasound effects on the release and activity of invertase from Aspergillus niger cultivated in a medium containing sucrose and peptone and in another with sugar-cane molasses and peptone were investigated. Irradiation was conducted for periods of 2 - 10 min. with waves of amplitude 20 and 40 using an ultrasound processor of 20 kHz. Product formation was determined as reducing equivalents formed by time units using 3,5-dinitrosalicylic acid. Total and specific activities of the culture supernatants were compared in the presence and absence of sonication. Both amplitudes promoted a significant increase of total invertase activity in the time periods investigated and the highest values were obtained with an amplitude of 20. Ultrasound irradiation caused cell disruption, thus releasing invertase and, after 4 min, activation of the enzyme also occurred. The best conditions for production, extraction and activation of invertase were in molasses medium containing peptone and irradiation with ultrasound waves at 20 for 8 min. This method showed high efficiency for the extraction and activation of invertase from A. niger as well as a great potential for use in industrial processes.

Corantes têxteis

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Arquitetura multiprocessada e reconfigurável para a síntese de redes de Petri em hardware

Uma arquitetura reconfigurável e multiprocessada para a implementação física de Redes de Petri foi desenvolvida em VHDL e mapeada sobre um FPGA. Convencionalmente, as Redes de Petri são transformadas em uma linguagem de descrição de hardware no nível de transferências entre registradores e um processo de síntese de alto nível é utilizado para gerar as funções booleanas e tabelas de transição de estado para que se possa, finalmente, mapeá-las num FPGA (Morris et al., 2000) (Soto and Pereira, 2001). A arquitetura proposta possui blocos lógicos reconfiguráveis desenvolvidos exclusivamente para a implementação dos lugares e das transições da rede, não sendo necessária a descrição da rede em níveis de abstração intermediários e nem a utilização de um processo de síntese para realizar o mapeamento da rede na arquitetura. A arquitetura permite o mapeamento de modelos de Redes de Petri com diferenciação entre as marcas e associação de tempo no disparo das transições, sendo composta por um arranjo de processadores reconfiguráveis, cada um dos quais representando o comportamento de uma transição da Rede de Petri a ser mapeada e por um sistema de comunicação, implementado por um conjunto de roteadores que são capazes de enviar pacotes de dados de um processador reconfigurável a outro. A arquitetura proposta foi validada num FPGA de 10.570 elementos lógicos com uma topologia que permitiu a implementação de Redes de Petri de até 9 transições e 36 lugares, atingindo uma latência de 15,4ns e uma vazão de até 17,12GB/s com uma freqüência de operação de 64,58MHz.

Simulation of free surface flows in a distributed memory environment

A parallel technique, for a distributed memory machine, based on domain decomposition for solving the Navier-Stokes equations in cartesian and cylindrical coordinates in two dimensions with free surfaces is described. It is based on the code by Tome and McKee (J. Comp. Phys. 110 (1994) 171-186) and Tome (Ph.D. Thesis, University of Strathclyde, Glasgow, 1993) which in turn is based on the SMAC method by Amsden and Harlow (Report LA-4370, Los Alamos Scientific Laboratory, 1971), which solves the Navier-Stokes equations in three steps: the momentum and Poisson equations and particle movement, These equations are discretized by explicit and 5-point finite differences. The parallelization is performed by splitting the computation domain into vertical panels and assigning each of these panels to a processor. All the computation can then be performed using nearest neighbour communication. Test runs comparing the performance of the parallel with the serial code, and a discussion of the load balancing question are presented. PVM is used for communication between processes. (C) 1999 Elsevier B.V. B.V. All rights reserved.

IEEE 1451-based multi-interface module (I2M) for industrial processes automation

This paper describes the implementation of a multi-interface module (I2M) for automation of industrial processes, based on the IEEE1451 standard. Process automation with I2M can communicate through either wires or using wireless communication, without any hardware or software changes. We used FPGA resources to implement the I2M functions FPGA, with a NIOS II processor and ZigBee communication system (IEEE802.15), as well as RS232 serial standard. Part of the project was done in the SOPC Builder environment, which gave the designer flexibility and speed to implement the NIOS II-based microprocessor system. To test the I2M implementation, a didactic Industrial Hydraulic Module (MHI-01) was used to simulate two industrial processes to be controlled by the system proposed.

Teaching real-time with a scheduler simulator

In this paper we describe a scheduler simulator for real-time tasks, RTsim, that can be used as a tool to teach real-time scheduling algorithms. It simulates a variety of preprogrammed scheduling policies for single and multi-processor systems and simple algorithm variants introduced by its user. Using RTsim students can conduct experiments that will allow them to understand the effects of each policy given different load conditions and learn which policy is better for different workloads. We show how to use RTsim as a learning tool and the results achieved with its application on the Real-Time Systems course taught at the B.Sc. on Computer Science at Paulista State University - Unesp - at Rio Preto.

Common architecture for discrete wavelet transform analysis and synthesis with sequential and constant processing elements

This paper adresses the problem on processing biological data such as cardiac beats, audio and ultrasonic range, calculating wavelet coefficients in real time, with processor clock running at frequency of present ASIC's and FPGA. The Paralell Filter Architecture for DWT has been improved, calculating wavelet coefficients in real time with hardware reduced to 60%. The new architecture, which also processes IDWT, is implemented with the Radix-2 or the Booth-Wallace Constant multipliers. Including series memory register banks, one integrated circuit Signal Analyzer, ultrasonic range, is presented.

Dynamic and isometric protocols of knee extension: Effect of fatigue on the EMG signal

The objective of this study was to analyze the electromyographic (EMG) signal behavior of rectus femoris (RF), vastus medialis (VM), vastus lateralis (VL) and biceps femoris (caput longum) (BFCL) from nine women during fatiguing dynamic and isometric knee extensions tests and to determine their EMGFT (Electromyographic Fatigue Threshold). Surface electrodes, biological signal acquisition module, analogical-digital converter board and specific software were used. The RMS (Root Mean Square) values obtained from concentric phase (80 to 30 degrees) of the dynamic knee extension andfrom isometric contraction were correlated with time on each load by linear regression analysis. The respective slopes were correlated with the correspondent load to determine the EMGFT. Force (Kgf) and median frequency - MF (Hz) obtained during MIVC (Maximal Isometric Voluntary Contraction) performed before and after the fatiguing tests were calculated in Matlab environment. The results demonstrated that the endurance time decreases with higher loads the EMG amplitude increase with time and was greater at higher loads, between muscles in dynamic exercise the RF and VL showed higher slopes, and in isometric exercise the VL showed the same behavior The EMGFT values were similar in both exercises; the force values predominantly decreased after fatiguing tests; however the MF only decreased after some loads. The protocols proposed allowed standardizing protocols at least to induce the fatigue process and to determine the EMGFT as an endurance indicative, which may be used to evaluate the effectiveness of rehabilitative or training interventions indicated to reduce muscle weakness and fatigue.

GDP 4.0 transfer to SGP 3.0 for SCIAMACHY no2 column processing: Verification with SDOAS / GDOAS prototype algorithms and delta-validation with NDACC / UV-visible network data

Until mid 2006, SCIAMACHY data processors for the operational retrieval of nitrogen dioxide (NO2) column data were based on the historical version 2 of the GOME Data Processor (GDP). On top of known problems inherent to GDP 2, ground-based validations of SCIAMACHY NO2 data revealed issues specific to SCIAMACHY, like a large cloud-dependent offset occurring at Northern latitudes. In 2006, the GDOAS prototype algorithm of the improved GDP version 4 was transferred to the off-line SCIAMACHY Ground Processor (SGP) version 3.0. In parallel, the calibration of SCIAMACHY radiometric data was upgraded. Before operational switch-on of SGP 3.0 and public release of upgraded SCIAMACHY NO2 data, we have investigated the accuracy of the algorithm transfer: (a) by checking the consistency of SGP 3.0 with prototype algorithms; and (b) by comparing SGP 3.0 NO2 data with ground-based observations reported by the WMO/GAW NDACC network of UV-visible DOAS/SAOZ spectrometers. This delta-validation study concludes that SGP 3.0 is a significant improvement with respect to the previous processor IPF 5.04. For three particular SCIAMACHY states, the study reveals unexplained features in the slant columns and air mass factors, although the quantitative impact on SGP 3.0 vertical columns is not significant.

Discrete wavelet transform signal analyzer

This paper addresses the problem of processing biological data, such as cardiac beats in the audio and ultrasonic range, and on calculating wavelet coefficients in real time, with the processor clock running at a frequency of present application-specified integrated circuits and field programmable gate array. The parallel filter architecture for discrete wavelet transform (DWT) has been improved, calculating the wavelet coefficients in real time with hardware reduced up to 60%. The new architecture, which also processes inverse DWT, is implemented with the Radix-2 or the Booth-Wallace constant multipliers. One integrated circuit signal analyzer in the ultrasonic range, including series memory register banks, is presented. © 2007 IEEE.

Back to school with tablets embedded in digital desks

A digital-desk pilot program, named One Laptop Per Child (OPLC), in Brazil uses a unique display design to provide an interactive interface developed to enhance education and minimize ergonomic concerns. The one-to-one computer strategy as proposed by Nicholas Negroponte is a way of circumventing the tragedy of the locked computer lab because it gives children full access to computers anytime. The OLPC program has focused on a solution that minimizes power consumption, which also limits the display's maximum size and processor performance because the LCD backlights are responsible for a significant part of the power consumption in laptops. The government has also developed a new type of low-cost tablet that is based on a resistive principle. High transparencies can be obtained in the 90% range in the tablet, while robustness is guaranteed by the outstanding tribological characteristics of Sn02 on glass.

Methodology proposal for acquisition of biotelemetric data in a real time

This work presents a methodological proposal for acquisition of biometric data through telemetry basing its development on a research-action and a case study. Nowadays, the qualified professionals of physical evaluation have to use specific devices to obtain biometric signals and data. These devices in the most of the time are high cost and difficult to use and handling. Therefore, the methodological proposal was elaborate in order to develop, conceptually, a bio telemetric device which could acquire the desirable biometric signals: oxymetry, biometrics, corporal temperature and pedometry which are essential for the area of physical evaluation. It was researched the existent biometrics sensors, the possible ways for the remote transmission of signals and the computer systems available so that the acquisition of data could be possible. This methodological proposal of remote acquisition of biometrical signals is structured in four modules: Acquisitor of biometrics data; Converser and transmitter of biometric signals; Receiver and Processor of biometrics signals and Generator of Interpretative Graphs. The modules aim the obtention of interpretative graphics of human biometric signals. In order to validate this proposal a functional prototype was developed and it is presented in the development of this work.

Conversor CA-CA de elevado fator de potência para aplicações com geradores de Ímã permanente

This paper proposes and describes a high power factor AC-AC converter for naval applications using Permanent Magnet Generator (PMG). The three-phase output voltages of the PMG vary from 260 Vrms (220 Hz) to 380 Vrms (360 Hz), depending on load conditions. The proposed converter consists of a Y-/ΔY power transformer, which provides electrical isolation between the PMG and remaining stages, and a twelve-pulse uncontrolled rectifier stage directly connected to a single-phase inverter stage, without the use of an intermediary DC-DC topology. This proposal results in more simplicity for the overall circuitry, assuring robustness, reliability and reduced costs. Furthermore, the multipulse rectifier stage is capable to provide high power factor and low total harmonic distortion for the input currents of the converter. The single-phase inverter stage was designed to operate with wide range of DC bus voltage, maintaining 120 Vrms, 60 Hz output. The control philosophy, implemented in a digital signal processor (DSP) which also contains protection routines, alows series connections between two identical converters, achieving 240 Vrms, 60 Hz total output voltage. Measured total harmonic distortion for the AC output voltage is lower than 2% and the input power factor is 0.93 at 3.6kW nominal load. © 2010 IEEE.