A Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration

Current nanometer technologies suffer within-die parameter uncertainties, varying workload conditions, aging, and temperature effects that cause a serious reduction on yield and performance. In this scenario, monitoring, calibration, and dynamic adaptation become essential, demanding systems with a collection of multi purpose monitors and exposing the need for light-weight monitoring networks. This paper presents a new monitoring network paradigm able to perform an early prioritization of the information. This is achieved by the introduction of a new hierarchy level, the threshing level. Targeting it, we propose a time-domain signaling scheme over a single-wire that minimizes the network switching activity as well as the routing requirements. To validate our approach, we make a thorough analysis of the architectural trade-offs and expose two complete monitoring systems that suppose an area improvement of 40% and a power reduction of three orders of magnitude compared to previous works.

On-chip Monitoring: A Light-Weight Interconnection Network Approach

Current nanometer technologies are subjected to several adverse effects that seriously impact the yield and performance of integrated circuits. Such is the case of within-die parameters uncertainties, varying workload conditions, aging, temperature, etc. Monitoring, calibration and dynamic adaptation have appeared as promising solutions to these issues and many kinds of monitors have been presented recently. In this scenario, where systems with hundreds of monitors of different types have been proposed, the need for light-weight monitoring networks has become essential. In this work we present a light-weight network architecture based on digitization resource sharing of nodes that require a time-to-digital conversion. Our proposal employs a single wire interface, shared among all the nodes in the network, and quantizes the time domain to perform the access multiplexing and transmit the information. It supposes a 16% improvement in area and power consumption compared to traditional approaches.

Validation of the SenseWear armband in circuit resistance training with different loads

The use of the SenseWear™ armband (SWA), an objective monitor of physical activity, is a relatively new device used by researchers to measure energy expenditure. These monitors are practical, relatively inexpensive and easy-to-use. The aim of the present study was to assess the validity of SWAs for the measurement of energy expenditure (EE) in circuit resistance training (CRT) at three different intensities in moderately active, healthy subjects. The study subjects (17 females, 12 males) undertook CRT at 30, 50 and 70% of the 15 repetition maximum for each exercise component wearing an SWA as well as an Oxycon Mobile (OM) portable metabolic system (a gold standard method for measuring EE). The EE rose as exercise intensity increased, but was underestimated by the SWAs. For women, Bland-Altman plots showed a bias of 1.13 ± 1.48 METs and 32.1 ± 34.0 kcal in favour of the OM system, while for men values of 2.33 ± 1.82 METs and 75.8 ± 50.8 kcal were recorded.

Desarrollo de una aplicación software para laboratorios remotos

Las prácticas en laboratorios forman una parte muy importante de la formación en todos los programas docentes. A pesar de esta importancia, la creación de un laboratorio no es una tarea fácil, ya que el hecho de equipar un laboratorio puede suponer un gran gasto económico, tanto inicial como posterior. Como solución, surge la educación a distancia, y en concreto los laboratorios virtuales, es decir, simulaciones de un laboratorio real utilizando modelos matemáticos. Por sus características y flexibilidad se han ido desarrollando laboratorios virtuales en el ámbito docente, pero no todas las áreas cuentan con tantas posibilidades o facilidades como en la electrónica. La mayoría de los laboratorios accesibles desde Internet que hay en la actualidad dentro de la enseñanza a distancia o formación online, son virtuales. El laboratorio que se ha desarrollado tiene como principal ventaja la realización de prácticas controlando instrumentos y circuitos reales de forma remota. El proyecto consiste en realizar un sistema software para implementar un laboratorio remoto en el área de la electrónica analógica, que pueda ser utilizado como complemento a las actividades formativas que se realizan en los laboratorios de los centros de enseñanza. El sistema completo también consta de un hardware controlado mediante buses de comunicación estándar, que permite la implementación de distintos circuitos analógicos, de tal forma que se pueda realizar prácticas sobre circuitos físicos reales. Para desarrollar un laboratorio lo más real posible, la aplicación que maneja el estudiante es un visor 3D. Con la utilización de un visor 3D lo que se pretende es tener un aumento de la realidad a la hora de realizar las prácticas de laboratorio remotamente. El sistema desarrollado cuenta con un sistema de comunicación basado en un modelo cliente-servidor: • Servidor: se encarga de procesar las acciones que realiza el cliente y controla y monitoriza los instrumentos y dispositivos del sistema hardware. • Cliente: sería el usuario final, que mediante un visor 3D comunica las acciones a realizar al servidor para que éste las procese. Practices in laboratories are a very important part of training in all educational programs. Despite this importance, the establishment of a laboratory is not an easy task, since the fact of equipping a laboratory can be a great economic budget, both initial and subsequent spending. As a solution, appears the education at distance (online), and in particular the virtual labs, namely simulations of a real laboratory by using mathematical models. Virtual laboratories in the field of teaching have been developed for its features and flexibility, but not all areas have so many possibilities or facilities as in electronics. The most accessible laboratories from the Internet that are currently accessible within the distance or e-learning (on-line) are virtual. The laboratory which has been developed has as a main advantage to make practices or exercises in the fact of controlling instruments and real circuits remotely. The project consists of making a software system in order to implement a remote laboratory in the area of analog electronics that can be used as a complement to the others training activities to be carried out. The complete system also consists of a controlled hardware by standard communication buses that allow the implementation of several analog circuits, in such a way that practices can control real physical circuits. To develop a laboratory as more realistic as possible, the application that manages the student is a 3D viewer. With the use of a 3D viewer, is intended to have an increase in reality when any student wants to access to laboratory practices remotely. The developed system has a communication system based on a model Client/Server: • Server: The system that handles actions provided by the client and controls and monitors the instruments and devices in the hardware system. • Client: The end user, which using a 3D viewer, communicates the actions to be performed at the server so that it will process them.

Student Reciprocal Peer Teaching as a Method for Active Learning: An Experience in an Electrotechnical Laboratory

Active learning is one of the most efficient mechanisms for learning, according to the psychology of learning. When students act as teachers for other students, the communication is more fluent and knowledge is transferred easier than in a traditional classroom. This teaching method is referred to in the literature as reciprocal peer teaching. In this study, the method is applied to laboratory sessions of a higher education institution course, and the students who act as teachers are referred to as ‘‘laboratory monitors.’’ A particular way to select the monitors and its impact in the final marks is proposed. A total of 181 students participated in the experiment, experiences with laboratory monitors are discussed, and methods for motivating and training laboratory monitors and regular students are proposed. The types of laboratory sessions that can be led by classmates are discussed. This work is related to the changes in teaching methods in the Spanish higher education system, prompted by the Bologna Process for the construction of the European Higher Education Area

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Temperature Sensor Placement Including Routing Overhead and Sampling Inaccuracies

Dynamic thermal management techniques require a collection of on-chip thermal sensors that imply a significant area and power overhead. Finding the optimum number of temperature monitors and their location on the chip surface to optimize accuracy is an NP-hard problem. In this work we improve the modeling of the problem by including area, power and networking constraints along with the consideration of three inaccuracy terms: spatial errors, sampling rate errors and monitor-inherent errors. The problem is solved by the simulated annealing algorithm. We apply the algorithm to a test case employing three different types of monitors to highlight the importance of the different metrics. Finally we present a case study of the Alpha 21364 processor under two different constraint scenarios.

Integrated electronic system for ultrasonic structural health monitoring

A fully integrated on-board electronic system that can perform in-situ structural health monitoring (SHM) of aircraft?s structures using specifically designed equipment for SHM based on guided wave ultrasonic method or Lamb waves? method is introduced. This equipment is called Phased Array Monitoring for Enhanced Life Assessment (PAMELA III) and is an essential part of overall PAMELA SHM? system. PAMELA III can generate any kind of excitation signals, acquire the response signals that propagate throughout the structure being tested, and perform the signal processing for damage detection directly on the structure without need to send the huge amount of raw signals but only the final SHM maps. It monitors the structure by means of an array of integrated Phased Array (PhA) transducers preferably bonded onto the host structure. The PAMELA III hardware for SHM mapping has been designed, built and subjected to laboratory tests, using aluminum and CFRP structures. The 12 channel system has been designed to be low weight (265 grams only), to have a small form factor, to be directly mounted above the integrated PhA transducers without need for cables and to be EMI protected so that the equipment can be taken on board an aircraft to perform required SHM analyses by use of embedded SHM algorithms. Moreover, the autonomous, automatic and on real-time working procedure makes it suitable for the avionic field, sending the corresponding alerts, maps and reports to external equipment.

Rural tourism quality in Spain. The "Q" mark.

The Spanish tourism stakchoiders (State Tourism Administration, public tourism agencies, hospitality sector, recreational sector, travel operators, other touristic business, etc.) have developed a very powerful and practical quality certification system for all the actors in the tourism sector, including all those actors and activities in the rural tourism sector, which traditionally do not have a proper tourism system. In this framework the Institute for Spanish Tourism Quality (ICTE) administers, manages and monitors the "Spanish Tourism Quality" "Q" Mark, as an exclusive brand that announces the quality of the activity and service provided by the certified tourist business.

Integración de baterías en sistemas fotovoltaicos conectados a red

La situación actual del mercado energético en España y el imparable aumento de las tasas por parte de las eléctricas, está fomentando la búsqueda de fuentes de energía alternativas que permitan a la población poder abastecerse de electricidad, sin tener que pagar unos costes tan elevados. Para cubrir esta necesidad, la energía fotovoltaica y sobretodo el autoconsumo con inyección a red o balance neto, está adquiriendo cada vez más importancia dentro del mundo energético. Pero la penetración de esta tecnología en la Red Eléctrica Española tiene un freno, la desconfianza por parte del operador de la red, ya que la fotovoltaica es una fuente de energía intermitente, que puede introducir inestabilidades en el sistema en caso de alta penetración. Por ello se necesita ganar la confianza de las eléctricas, haciendo que sea una energía predecible, que aporte potencia a la red eléctrica cuando se le pida y que opere participando en la regulación de la frecuencia del sistema eléctrico. Para tal fin, el grupo de investigación de Sistemas Fotovoltaicos, perteneciente al IES de la UPM, está llevando a cabo un proyecto de investigación denominado PV CROPS, financiado por la Comisión Europea, y que tiene por objetivo desarrollar estas estrategias de gestión. En este contexto, el objetivo de este Proyecto Fin de Carrera consiste en implementar un Banco de Ensayos con Integración de Baterías en Sistemas FV Conectados a Red, que permita desarrollar, ensayar y validar estas estrategias. Aprovechando la disponibilidad para usar el Hogar Digital, instalado en la EUITT de la UPM, hemos montado el banco de ensayos en un laboratorio contiguo, y así, poder utilizar este Hogar como un caso real de consumos energéticos de una vivienda. Este banco de ensayos permitirá obtener información de la energía generada por la instalación fotovoltaica y del consumo real de la "casa" anexa, para desarrollar posteriormente estrategias de gestión de la electricidad. El Banco de Ensayos está compuesto por tres bloques principales, interconectados entre sí:  Subsistema de Captación de Datos y Comunicación. Encargado de monitorizar los elementos energéticos y de enviar la información recopilada al Subsistema de Control. Formado por analizadores de red eléctrica, monofásicos y de continua, y una pasarela orientada a la conversión del medio físico Ethernet a RS485.  Subsistema de Control. Punto de observación y recopilación de toda la información que proviene de los elementos energéticos. Es el subsistema donde se crearán y se implementarán estrategias de control energético. Compuesto por un equipo Pxie, controlador empotrado en un chasis de gama industrial, y un equipo PC Host, compuesto por una workstation y tres monitores.  Subsistema de Energía. Formado por los elementos que generan, controlan o consumen energía eléctrica, en el Banco de Ensayos. Constituido por una pérgola FV, un inversor, un inversor bidireccional y un bloque de baterías. El último paso ha sido llevar a cabo un Ejemplo de Aplicación Práctica, con el que hemos probado que el Banco de Ensayos está listo para usarse, es operativo y completamente funcional en operaciones de monitorización de generación energética fotovoltaica y consumo energético. ABSTRACT. The current situation of the energetic market in Spain and the unstoppable increase of the tax on the part of the electrical companies, is promoting the search of alternative sources of energy that allow to the population being able to be supplied of electricity, without having to pay so high costs. To meet this need, the photovoltaic power and above all the self-consumption with injection to network, it is increasingly important inside the energetic world. It allows to the individual not only to pay less for the electricity, in addition it allows to obtain benefits for the energy generated in his own home. But the penetration of this technology in the Electrical Spanish Network has an obstacle, the distrust on the part of the operator of the electrical network, due to the photovoltaic is an intermittent source of energy, which can introduce instabilities in the system in case of high penetration. Therefore it´s necessary to reach the confidence of the electricity companies, making it a predictable energy, which provides with power to the electrical network whenever necessary and that operates taking part in the regulation of the frequency of the electric system. For such an end, the group of system investigation Photovoltaic, belonging to the IES of the UPM, there is carrying out a project of investigation named PV CROPS, financed by the European Commission, and that has for aim to develop these strategies of management. In this context, the objective of this Senior Thesis consists in implementing a Bank of Tests with Integration of Batteries in Photovoltaic Systems Connected to Network, which allows developing, testing and validating these strategies. Taking advantage of the availability to use the Digital Home installed in the EUITT of the UPM, we have mounted the bank of tests in a contiguous laboratory to use this Home as a real case of energetic consumptions of a house. This bank of tests will allow obtaining information of the energy generated by the photovoltaic installation and information of the royal consumption of the attached "house", to develop later strategies of management of the electricity. The Bank of Tests is composed by three principal blocks, interconnected each other:  Subsystem of Gathering of data and Communication. In charge of monitoring the energetic elements and sending the information compiled to the Subsystem of Control. Formed by power analyzers, AC and DC, and a gateway for the conversion of the Ethernet physical medium to RS485.  Subsystem of Control. Point of observation and compilation of all the information that comes from the energetic elements. It is the subsystem where there will be created and there will be implemented strategies of energetic control. Composed of a Pxie, controller fixed in an industrial range chassis, and a PC Host, formed by a workstation and three monitors.  Subsystem of Energy. Formed by the elements of generating, controlling or consuming electric power, in the Bank of Tests. Made of photovoltaic modules, an inverter, a twoway inverter and a batteries block. The last step has been performing an Example of Practical Application we have proved that the Bank of Tests is ready to be used, it´s operative and fully functional in monitoring operations of energetic photovoltaic generation and energetic consumption.

An energy efficient adaptive HELLO algorithm for mobile ad hoc networks

HELLO protocol or neighborhood discovery is essential in wireless ad hoc networks. It makes the rules for nodes to claim their existence/aliveness. In the presence of node mobility, no fix optimal HELLO frequency and optimal transmission range exist to maintain accurate neighborhood tables while reducing the energy consumption and bandwidth occupation. Thus a Turnover based Frequency and transmission Power Adaptation algorithm (TFPA) is presented in this paper. The method enables nodes in mobile networks to dynamically adjust both their HELLO frequency and transmission range depending on the relative speed. In TFPA, each node monitors its neighborhood table to count new neighbors and calculate the turnover ratio. The relationship between relative speed and turnover ratio is formulated and optimal transmission range is derived according to battery consumption model to minimize the overall transmission energy. By taking advantage of the theoretical analysis, the HELLO frequency is adapted dynamically in conjunction with the transmission range to maintain accurate neighborhood table and to allow important energy savings. The algorithm is simulated and compared to other state-of-the-art algorithms. The experimental results demonstrate that the TFPA algorithm obtains high neighborhood accuracy with low HELLO frequency (at least 11% average reduction) and with the lowest energy consumption. Besides, the TFPA algorithm does not require any additional GPS-like device to estimate the relative speed for each node, hence the hardware cost is reduced.

Enhancement of a body area network to support smart health monitoring at the digital home

The deployment of home-based smart health services requires effective and reliable systems for personal and environmental data management. ooperation between Home Area Networks (HAN) and Body Area Networks (BAN) can provide smart systems with ad hoc reasoning information to support health care. This paper details the implementation of an architecture that integrates BAN, HAN and intelligent agents to manage physiological and environmental data to proactively detect risk situations at the digital home. The system monitors dynamic situations and timely adjusts its behavior to detect user risks concerning to health. Thus, this work provides a reasoning framework to infer appropriate solutions in cases of health risk episodes. Proposed smart health monitoring approach integrates complex reasoning according to home environment, user profile and physiological parameters defined by a scalable ontology. As a result, health care demands can be detected to activate adequate internal mechanisms and report public health services for requested actions.

Visualizador de programas Java concurrentes

El presente trabajo fin de grado, que, a partir de ahora, denominaré TFG, consiste en elaborar una monitorización de programas concurrentes en lenguaje Java, para que se visualicen los eventos ocurridos durante la ejecución de los dichos programas. Este trabajo surge en el marco de la asignatura “Concurrencia” de la Escuela Técnica Superior de Ingeniería Informática de la Universidad Politécnica de Madrid, impartida por D. Julio Mariño y D. Ángel Herranz. El objetivo principal de este proyecto es crear una herramienta para el aprendizaje de la asignatura de concurrencia, facilitando la comprensión de los conceptos teóricos, de modo que puedan corregir los posibles errores que haya en sus prácticas. en este proyecto se expone el desarrollo de una librería de visualización de programas concurrentes programados en Java usando un formalismo gráfico similar al empleado en la asignatura. Además esta librería da soporte a los mecanismos de sincronización usados en las prácticas de la asignatura: la librería Monitor (desarrollada por los profesores de la asignatura, D. Ángel Herranz y D. Julio Mariño) y la librería JCSP (Universidad de Kent). ---ABSTRACT---This Bachelor Thesis addresses the problem of monitoring a Java program in order to trace and visualize a certain set of events produced during the execution of concurrent Java programs. This work originates in the subject "Concurrency" of the Computer Science and Engineering degree of our University. The main goal of this work is to have a tool that helps students learning the subject, so they can better understand the core concepts and correct common mistakes in the course practical work. We have implemented a library for visualizing concurrent Java programsusing a graphical notation similar to the one used in class, which supports the design of concurrent programs whose synchronization mechanisms are either monitors(using the Monitor package) or CSP(as implemented in the JCSP library from Kent University).

SVD Applied to Voltage Sag State Estimation

The method presented in this paper addresses the problem of voltage sag state estimation (VSSE). The problem consists in estimating the voltage sags frequency at non-monitored buses from the number of sags measured at monitored sites. Usually, due to limitations on the number of available voltage sag monitors, this is an underdetermined problem. In this approach, the mathematical formulation presented is based on the fault positions concept and is solved by means of the Singular Value Decomposition (SVD) technique. The proposed estimation method has been validated by using the IEEE 118 test system and the results obtained have been very satisfactory.

Sistema de protección contra incendios de un parque de almacenamiento de líquidos petrolíferos

Los procesos relacionados con el almacenamiento y manipulación de productos petrolíferos, conllevan siempre determinados riesgos de incendio que dependen básicamente de las propiedades físicas y químicas de los productos, y hacen indispensable la adopción de importantes medidas de seguridad contra incendios. Esto es debido a que las consecuencias previsibles en caso de la producción y expansión del incendio son tan graves que aconsejan la instalación de medios más potentes de lucha contra incendios, que los simples extintores manuales. En base a ello, el presente proyecto pretende definir y desarrollar una propuesta de diseño del sistema de protección contra incendios en la zona de almacenamiento de una planta de almacenamiento de líquidos petrolíferos. La planta almacena Gasóleo, Gasolina y Queroseno de Aviación en ocho tanques atmosféricos de techo fijo situados en un único cubeto de retención. Se desarrolla un extenso estudio de los requisitos normativos para este tipo de casos, y en consecuencia, se calcula y clasifica el nivel de riesgo intrínseco de incendio en la zona estudiada, a partir de su carga de fuego ponderada y corregida. Además, se muestra la distribución de los tanques en el cubeto, basada en el cálculo de las distancias de seguridad entre cada uno de ellos y con el exterior. A partir de ello, el proyecto se centra en el cálculo de los valores de descarga de agua de refrigeración, requeridos en las boquillas de agua pulverizada e hidrantes exteriores de alrededor de la zona de riesgo; de espuma física para hidrocarburos, en las cámaras de espuma de la parte superior de la envolvente de los tanques, y en los monitores auxiliares de descarga de espuma, de la zona del cubeto de retención. Los objetivos, métodos y bases de cálculo se recogen en la memoria del proyecto. Además se incluye, la planificación temporal con MS Project, de la implementación del proyecto; la elección de los equipos que componen los sistemas, el presupuesto asociado y los planos de distribución de la planta y del flujo de tuberías propuesto. ABSTRACT Fire protection units and equipment are necessary on processes and operations related to storage and handling of petroleum products, because of their flammable and combustible properties. In case a hazard of fire from petroleum products is materialized, huge consequences are to be expected. To reduce losses, facilities should be equipped with appropriate protection. Based on that, this project seeks to define and develop the fire protection system design for a petroleum liquids storage installation. The plant stores Gasoil, Gasoline, and aviation Kerosene in eight fixed roof atmospheric tanks. A complete study of the fire protection regulations is carried out and, as a result, the studied area’s risk level is determined from its fire load density. The calculation of the minimum shell-to-shell spacing of adjacent aboveground storage tanks and external equipment, is also determined for a correct distribution of tanks in the bunded area. Assuming that, the design includes calculations of required discharge of water for spray nozzles and hydrants, and required discharge of foam from foam chambers and foam monitors. Objectives, methodology and calculation basis are presented on the project technical report; which also includes project scheduling with MS. Project software, the selection of system components and equipment, related budget and lay out of installation and piping.