Air traffic control with an expected value criterion

in this contribution we discuss a stochastic framework for air traffic conflict resolution. The conflict resolution task is posed as the problem of optimizing an expected value criterion. Optimization is carried out by Monte Carlo Markov Chain (MCMC) simulation. A numerical example illustrates the proposed strategy. Copyright © 2005 IFAC.

Monte Carlo optimization strategies for air-traffic control

The safety of the flights, and in particular conflict resolution for separation assurance, is one of the main tasks of Air Traffic Control. Conflict resolution requires decision making in the face of the considerable levels of uncertainty inherent in the motion of aircraft. We present a Monte Carlo framework for conflict resolution which allows one to take into account such levels of uncertainty through the use of a stochastic simulator. A simulation example inspired by current air traffic control practice illustrates the proposed conflict resolution strategy. Copyright © 2005 by the American Institute of Aeronautics and Astronautics, Inc. All rights reserved.

Comparison of stochastic methods for control in air traffic management

This paper provides a direct comparison of two stochastic optimisation techniques (Markov Chain Monte Carlo and Sequential Monte Carlo) when applied to the problem of conflict resolution and aircraft trajectory control in air traffic management. The two methods are then also compared to another existing technique of Mixed-Integer Linear Programming which is also popular in distributed control. © 2011 IFAC.

Effects of longer heavy vehicles on traffic congestion

Two-lane, "microscopic" (vehicle-by-vehicle) simulations of motorway traffic are developed using existing models and validated using measured data from the M25 motorway. An energy consumption model is also built in, which takes the logged trajectories of simulated vehicles as drive-cycles. The simulations are used to investigate the effects on motorway congestion and fuel consumption if "longer and/or heavier vehicles" (LHVs) were to be permitted in the UK. Baseline scenarios are simulated with traffic composed of cars, light goods vehicles and standard heavy goods vehicles (HGVs). A proportion of conventional articulated HGVs is then replaced by a smaller number of LHVs carrying the same total payload mass and volume. Four LHV configurations are investigated: an 18.75 m, 46 t longer semi-trailer (LST); 25.25 m, 50 t and 60 t B-doubles and a 34 m, 82 t A-double. Metrics for congestion, freight fleet energy consumption and car energy consumption are defined for comparing the scenarios. Finally, variation of take-up level and LHV engine power for the LST and A-double are investigated. It is concluded that: (a) LHVs should reduce congestion particularly in dense traffic, however, a low mean proportion of freight traffic on UK roads and low take-up levels will limit this effect to be almost negligible; (b) LHVs can significantly improve the energy efficiency of freight fleets, giving up to a 23% reduction in fleet energy consumption at high take-up levels; (c) the small reduction in congestion caused by LHVs could improve the fuel consumption of other road users by up to 3% in dense traffic, however in free-flowing traffic an opposite effect occurs due to higher vehicle speeds and aerodynamic losses; and (d) underpowered LHVs have potential to generate severe congestion, however current manufacturers' recommendations appear suitable. © 2013 IMechE.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

adaptive location update mechanism for network-constrained moving objects in changeful traffic conditions

Natl Chiao Tung Univ, Dept Comp Sci