A simulation model of body contact structure in PD SOI analogue circuit

As a solution of accurate simulation of the body effect in PD SOI analogue circuit, a simulation model of distributed body contact resistance and parasitical capacitance is presented. Based on this model, we have designed and simulated a sense amplifier that applied to V a 0.8um PD SOI 64K SRAM.

A silicon capacitive microphone based on oxidized porous silicon sacrificial technology

In this paper, a new capacitive microphone fabrication technology is proposed. It describes using the oxidized porous silicon sacrificial technology to make air gap and using KOH etching technique to make the backplate containing acoustic holes based on the principle that the heavy p(+)-doping silicon can be nearly etched in KOH solution. The innovation of the method is using oxidized porous silicon technology. The sensitivity of the fabricated microphone is from -55dB ( 1.78mV/Pa) to -45dB (5.6mV/Pa) in the frequency range of 500Hz to 25kHz. Its cut-off frequency is higher than 20kHz.

A practical package technique for FBG-based temperature independent sensor

A practical package technique for temperature independent Fiber Bragg grating sensor is proposed. A uniform strength cantilever with two FBG attached on the upper and lower surfaces was utilized as the key element. By detecting two wavelengths differential output, the applied force can be obtained and temperature effects can be eliminated. Experiment results show the sensor has linear response and output signal uctuates less than 12pm as temperature changes from -10 degrees C to 50 degrees C. The maximum thermal error is less than 0.3% of the full measurement range.

Structural optimizations of SOI-based single-mode rib waveguide bends

Effects of structure parameters on bend loss of rib silicon-on-insulator (Sol) bend waveguides have been analyzed by means of effective index method (EIM) and 2D bend loss formula. The simulation results indicate that the bend loss decreases with the increase of bend radius and waveguide width, as well as with the decrease of the step factor of the rib waveguide. Moreover, the optional structure parameters have been found when bend waveguides are single-mode.

A low power consumption thermo-optic variable optical attenuator based on SOI material

A SOI thenno-optic variable optical attenuator with U-grooves based on a multimode interference coupler principle is fabricated. The dynamic attenuation range is 0 to 29 dB; at the wavelength range between 1510 nm and 1610nm, and the maximum power consumption is only l30mW. Compared to the variable optical attenuator without U-groove, the maximum power consumption decreases more than 230mW

The effect of Fabry-Perot interference on the packaging of SOI-based optoelectronic devices

During the packaging of optoelectrome device, a problem always met is the instability of output power. The main effect causing this problem, Fabry-Perot interference, is discussed in this paper. Both theoretical analysis and experimental test are carried out and in good agreement. As an example of avoiding the disadvantage of Fabry-Perot interference, the packaging process of Silicon-on-Insulator (SOI) based Variable Optical Attenuator(VOA) is shown at last.

Improved diphasic nc-si/a-si : H I-layer materials using PECVD

Two series of films has been prepared by using a new regime of plasma enhanced chemical vapor deposition (PECVD) in the region adjacent to the phase transition from amorphous to crystalline state. The photoelectronic properties of the films have been investigated as a function of crystalline fraction. In comparison with typical a-Si:H, these diphasic films with a crystalline fraction less than 0.3 show a similar optical absorption coefficient, higher mobility life-time product ( LT) and higher stability upon light soaking. By using the diphasic nc-Si/a-Si films as the intrinsic layer, a p-i-n junction solar cell has been prepared with an initial efficiency of 9. 10 % and a stabilized efficiency of 8.56 % (AM 1.5, 100 mW/cm(2)).

Homoepitaxial growth and MOS structures of 4H-SiC on off oriented n-type (0001)Si-faces

Homoepitaxial growth of 4H-SiC on off-oriented n-type Si-face (0001) substrates was performed in a home-made hot-wall low pressure chemical vapor deposition (LPCVD) reactor with SiH4 and C2H4 at temperature of 1500 C and pressure of 20 Torr. The surface morphology and intentional in-situ NH3 doping in 4H-SiC epilayers were investigated by using atomic force microscopy (AFM) and secondary ion mass spectroscopy (SIMS). Thermal oxidization of 4H-SiC homoepitaxial layers was conducted in a dry O-2 and H-2 atmosphere at temperature of 1150 C. The oxide was investigated by employing x-ray photoelectron spectroscopy (XPS). 4H-SiC MOS structures were obtained and their C-V characteristics were presented.

Hetero-epitaxial growth of ZnO films on silicon by low-pressure metal organic chemical vapor deposition

Quality ZnO films were successfully grown on Si(100) substrate by low-pressure metal organic chemical vapor deposition method in temperature range of 300-500 degrees C using DEZn and N2O as precursor and oxygen source respectively. The crystal structure, optical properties and surface morphology of ZnO films were characterized by X-ray diffraction, optical refection and atomic force microscopy technologies. It was demonstrated that the crystalline structure and surface morphology of ZnO films strongly depend on the growth temperature.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

A Novel 0.72-6.2GHz Continuously-Tunable Delta Sigma Fractional-N Frequency Synthesizer

This paper presents a wideband Delta Sigma-based fractional-N synthesizer with three integrated quadrature VCOs for multiple-input multiple-output (MIMO) wireless communication applications. It continuously covers a wide range frequency from 0.72GHz to 6.2GHz that is suitable for multiple communication standards. The synthesizer is designed in 0.13-um RE CMOS process. The dual clock full differential multi-modulus divide (MMD) with low power consumption can operate over 9GHz under the worst condition. In the whole range frequency from 0.72GHz to 6.2GHz, the maximal tuning range of the QVCOs reaches 33.09% and their phase noise is -119d8/Hz similar to 124d8/Hz @1MHz. Its current is less than 12mA at a 1.2V voltage supply when it operates at the highest frequency of 6.2GHz.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

RSA-Based Password-Authenticated Key Exchange, Revisited

The RSA-based Password-Authenticated Key Exchange (PAKE) protocols have been proposed to realize both mutual authentication and generation of secure session keys where a client is sharing his/her password only with a server and the latter should generate its RSA public/private key pair (e, n), (d, n) every time due to the lack of PKI (Public-Key Infrastructures). One of the ways to avoid a special kind of off-line (so called e-residue) attacks in the RSA-based PAKE protocols is to deploy a challenge/response method by which a client verifies the relative primality of e and φ(n) interactively with a server. However, this kind of RSA-based PAKE protocols did not give any proof of the underlying challenge/response method and therefore could not specify the exact complexity of their protocols since there exists another security parameter, needed in the challenge/response method. In this paper, we first present an RSA-based PAKE (RSA-PAKE) protocol that can deploy two different challenge/response methods (denoted by Challenge/Response Method1 and Challenge/Response Method2). The main contributions of this work include: (1) Based on the number theory, we prove that the Challenge/Response Method1 and the Challenge/Response Method2 are secure against e-residue attacks for any odd prime e; (2) With the security parameter for the on-line attacks, we show that the RSA-PAKE protocol is provably secure in the random oracle model where all of the off-line attacks are not more efficient than on-line dictionary attacks; and (3) By considering the Hamming weight of e and its complexity in the RSA-PAKE protocol, we search for primes to be recommended for a practical use. We also compare the RSA-PAKE protocol with the previous ones mainly in terms of computation and communication complexities.

匿名凭证与匿名口令认证技术研究

随着隐私保护越来越为人们所关注，对匿名认证技术的研究已经成为学术领域的一个热点。本文主要着眼于匿名认证中的匿名凭证与匿名口令认证密钥协商。 在对匿名凭证技术的研究中，本文重点分析了防止凭证出借与凭证匿名更新两个匿名凭证系统性质的实现。 凭证出借是指匿名凭证系统中，用户可以随意将自己的凭证与他人共享，从而使多人可以同时使用一个凭证。本文提出一种新的防止凭证出借方法，并给出一个具体的实现方案。该方法将凭证出借与用户隐私联系起来，通过凭证本身实现防止凭证出借。凭证匿名更新则是指凭证内容进行更新时，凭证颁发方只能知道变更的内容信息，不知道其他任何信息。本文提出一种新的实现方法，在原有凭证的基础上，用相对较少的计算量来实现对凭证内容的更新，使用户匿名得到一个新的凭证。 在对匿名口令认证密钥协商的研究中，本文首先提出了两个攻击方案：针对Shin等人的TAP(t≥2)协议的内部假扮攻击和针对TAP(t≥2)协议以及Viet等人的k-out-of-n APAKE协议的离线字典攻击。前者破坏了协议的认证性，内部攻击者可以假扮服务器与用户建立会话密钥。后者破坏了协议最基本的对口令的安全保护，使得内部攻击者可以离线猜测组内所有用户口令。然后，本文提出了一个新的两方的匿名口令认证密钥协商协议：NAPAKE，并在Square Computational Diffiee-Hellman困难假设以及Decision Inverted-Additive Diffie-Hellman困难假设下证明其安全性。同时，还进一步将其扩展为D-NAPAKE协议，以实现多方的匿名口令认证密钥协商，该协议可以抵抗上面的两个攻击。

2 x 2 electrooptical switch in silicon-on-insulator waveguide

A 2 x 2 Mach-Zehnder interferometer electrooptical switch integrated in silicon-on-insulator using multimode interference 3-dB couplers as splitter and combiner has been proposed and fabricated. Free carriers plasma dispersion effect was utilized to realize light modulation in silicon. Switching operation was achieved at an injection current of 358mA and which can be much reduced by optimizing the PIN structure and improving fabrication process. Extinction ratio of 7.7dB and crosstalk of 4.8dB has been observed.