Real time maximum power conversion tracking and resonant frequency modification for high power piezoelectric ultrasound transducer

Piezoelectric ultrasound transducers are commonly used to convert mechanical energy to electrical energy and vice versa. The transducer performance is highly affected by the frequency at which it is excited. If excitation frequency and main resonant frequency match, transducers can deliver maximum power. However, the problem is that main resonant frequency changes in real time operation resulting in low power conversion. To achieve the maximum possible power conversion, the transducer should be excited at its resonant frequency estimated in real time. This paper proposes a method to first estimate the resonant frequency of the transducer and then tunes the excitation frequency accordingly in real time. The measurement showed a significant difference between the offline and real time resonant frequencies. Also, it was shown that the maximum power was achieved at the resonant frequency estimated in real time compare to the one measured offline.

Reversible Conversion of Dominant Polarity in Ambipolar Polymer/Graphene Oxide Hybrids

The possibility to selectively modulate the charge carrier transport in semiconducting materials is extremely challenging for the development of high performance and low-power consuming logic circuits. Systematical control over the polarity (electrons and holes) in transistor based on solution processed layer by layer polymer/graphene oxide hybrid system has been demonstrated. The conversion degree of the polarity is well controlled and reversible by trapping the opposite carriers. Basically, an electron device is switched to be a hole only device or vice versa. Finally, a hybrid layer ambipolar inverter is demonstrated in which almost no leakage of opposite carrier is found. This hybrid material has wide range of applications in planar p-n junctions and logic circuits for high-throughput manufacturing of printed electronic circuits.

A Combination of Hexagonal and 12-Sided Polygonal Voltage Space Vector PWM Control for IM Drives Using Cascaded Two-Level Inverters

This paper proposes a multilevel inverter configuration which produces a hexagonal voltage space vector structure in the lower modulation region and a 12-sided polygonal space vector structure in the overmodulation region. A conventional multilevel inverter produces 6n plusmn 1 (n = odd) harmonics in the phase voltage during overmodulation and in the extreme square-wave mode of operation. However, this inverter produces a 12-sided polygonal space vector location, leading to the elimination of 6n plusmn 1 (n = odd) harmonics in the overmodulation region extending to a final 12-step mode of operation with a smooth transition. The benefits of this arrangement are lower losses and reduced torque pulsation in an induction motor drive fed from this converter at higher modulation indexes. The inverter is fabricated by using three conventional cascaded two-level inverters with asymmetric dc-bus voltages. A comparative simulation study of the harmonic distortion in the phase voltage and associated losses in conventional multilevel inverters and that of the proposed inverter is presented in this paper. Experimental validation on a prototype shows that the proposed converter is suitable for high-power applications because of low harmonic distortion and low losses.

A Multilevel Inverter with Hexagonal and 12-sided Polygonal Space Vector Structure for Induction Motor Drive

This paper proposes a multilevel inverter which produces hexagonal voltage space vector structure in lower modulation region and a 12-sided polygonal space vector structure in the over-modulation region. Normal conventional multilevel inverter produces 6n +/- 1 (n=odd) harmonics in the phase voltage during over-modulation and in the extreme square wave mode operation. However, this inverter produces a 12-sided polygonal space vector location leading to the elimination of 6n 1 (n=odd) harmonics in over-modulation region extending to a final 12-step mode operation. The inverter consists of three conventional cascaded two level inverters with asymmetric dc bus voltages. The switching frequency of individual inverters is kept low throughout the modulation index. In the low speed region, hexagonal space phasor based PWM scheme and in the higher modulation region, 12-sided polygonal voltage space vector structure is used. Experimental results presented in this paper shows that the proposed converter is suitable for high power applications because of low harmonic distortion and low switching losses.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

Negative sequence compensation within fundamental positive sequence reference frame for a stiff micro-grid generation in a wind power system using slip ring induction machine

An isolated wind power generation scheme using slip ring induction machine (SRIM) is proposed. The proposed scheme maintains constant load voltage and frequency irrespective of the wind speed or load variation. The power circuit consists of two back-to-back connected inverters with a common dc link, where one inverter is directly connected to the rotor side of SRIM and the other inverter is connected to the stator side of the SRIM through LC filter. Developing a negative sequence compensation method to ensure that, even under the presence of unbalanced load, the generator experiences almost balanced three-phase current and most of the unbalanced current is directed through the stator side converter is the focus here. The SRIM controller varies the speed of the generator with variation in the wind speed to extract maximum power. The difference of the generated power and the load power is either stored in or extracted from a battery bank, which is interfaced to the common dc link through a multiphase bidirectional fly-back dc-dc converter. The SRIM control scheme, maximum power point extraction algorithm and the fly-back converter topology are incorporated from available literature. The proposed scheme is both simulated and experimentally verified.

Analysis and Improvements to the Green Falcon Solar Powered UAV

There has recently been a rapidly increasing interest in solar powered UAVs. With the emergence of high power density batteries, long range and low-power micro radio devices, airframes, and powerful micro-processors and motors, small/micro UAVs have become applicable in civilian applications such as remote sensing, mapping, traffic monitoring, search and rescue. The Green Falcon UAV is an innovative project from Queensland University of Technology and has been developed and tested during these past years. It comprises a wide range of subsystems to be analyses and studied such as Solar Panel Cells, Gas sensor, Aerodynamics of the wing and others. Previous test however, resulted in damage to the solar cells and some of the subsystems including motor and ESC. This report describes the repair and verification process followed to improve the efficiency of the Green Falcon UAV. The report shows some of the results obtained in previous static and flight tests as well as some of recommendations.

Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders

Run-time interoperability between different applications based on H.264/AVC is an emerging need in networked infotainment, where media delivery must match the desired resolution and quality of the end terminals. In this paper, we describe the architecture and design of a polymorphic ASIC to support this. The H.264 decoding flow is partitioned into modules, such that the polymorphic ASIC meets the design goals of low-power, low-area, high flexibility, high throughput and fast interoperability between different profiles and levels of H.264. We demonstrate the idea with a multi-mode decoder that can decode baseline, main and high profile H.264 streams and can interoperate at run.time across these profiles. The decoder is capable of processing frame sizes of up to 1024 times 768 at 30 fps. The design synthesized with UMC 0.13 mum technology, occupies 250 k gates and runs at 100 MHz.

RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

The Power of Bootstrap Tests of Cointegration Rank with Financial Time Series

Bootstrap likelihood ratio tests of cointegration rank are commonly used because they tend to have rejection probabilities that are closer to the nominal level than the rejection probabilities of the correspond- ing asymptotic tests. The e¤ect of bootstrapping the test on its power is largely unknown. We show that a new computationally inexpensive procedure can be applied to the estimation of the power function of the bootstrap test of cointegration rank. The bootstrap test is found to have a power function close to that of the level-adjusted asymp- totic test. The bootstrap test estimates the level-adjusted power of the asymptotic test highly accurately. The bootstrap test may have low power to reject the null hypothesis of cointegration rank zero, or underestimate the cointegration rank. An empirical application to Euribor interest rates is provided as an illustration of the findings.

Synthesis, magnetic and electrical properties of Fe-containing SiO2 nanocomposite

Nanocrystalline Fe powders were synthesized by transmetallation reaction and embedded in silica to form Fe-SiO2 nanocomposite. Thermomagnetic study of the as-prepared Fe sample indicates the presence of Fe3O4 and Fe particles. Oxidation studies of Fe and Fe-SiO2 show an increased thermal stability of Fe-SiO2 nanocomposite over pure Fe. The Fe-SiO2 shows an enhanced oxidation temperature (i.e., 780 K) and a maximum saturation magnetization value of (135 emu/g) with 64 wt.% of Fe content in silica. Electrical and dielectric behaviour of the Fe-SiO2 nanocomposite has been investigated as a function of temperature and frequency. Low frequency ac conductivity and dielectric constants were found to be influenced by desorptions of chemisorbed moisture. High saturation magnetization, thermal stability, frequency-dependent conductivity and low power loss make Fe-silica a promising material for high frequency applications. (C) 2010 Elsevier B.V. All rights reserved.

OPSM - Opportunistic Power Save mode for Infrastructure IEEE 802.11 WLAN

We focus on the energy spent in radio communication by the stations (STAs) in an IEEE 802.11 infrastructure WLAN. All the STAs are engaged in web browsing, which is characterized by a short file downloads over TCP, with short duration of inactivity or think time in between two file downloads. Under this traffic, Static PSM (SPSM) performs better than CAM, since the STAs in SPSM can switch to low power state (sleep) during think times while in CAM they have to be in the active state all the time. In spite of this gain, performance of SPSM degrades due to congestion, as the number of STAs associated with the access point (AP) increases. To address this problem, we propose an algorithm, which we call opportunistic PSM (OPSM). We show through simulations that OPSM performs better than SPSM under the aforementioned TCP traffic. The performance gain achieved by OPSM over SPSM increases as the mean file size requested by the STAs or the number of STAs associated with the AP increases. We implemented OPSM in NS-2.33, and to compare the performance of OPSM and SPSM, we evaluate the number of file downloads that can be completed with a given battery capacity and the average time taken to download a file.

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

A portable battery-operated chip thermocycler based on induction heating

A microchip thermocycler, fabricated from silicon and Pyrex #7740 glass, is described. Usual resistive heating has been replaced by induction heating, leading to much simpler fabrication steps. Heating and cooling rates of 6.5 and 4.2 degreesC/s, respectively have been achieved, by optimising the heater dimensions and heating frequency (similar to200 kHz). Four devices are mounted on a heater, resulting in low power consumption (similar to 1.4 W per device on the average). Using simple on-off electronic temperature control, a temperature stability within -0.2 degreesC is achieved. Features such as induction heating, good temperature control, battery operation, and low power consumption make the device suitable for portable applications, particularly in polymerase chain reaction (PCR) systems. (C) 2002 Elsevier Science B.V. All rights reserved.

Electrochemical studies of polyaniline in a gel polymer electrolyte - High energy and high power characteristics of a solid-state redox supercapacitor

Studies on redox supercapacitors employing electronically conducting polymers are of great importance for hybrid power sources and pulse power applications. In the present study, polyaniline (PANI) has been potentiodynamically deposited on stainless steel substrate and characterized in a gel polymer electrolyte (GPE). Use of the GPE facilitates a voltage limit of the capacitor to 1 V, instead of 0.75 V in aqueous electrolytes. From charge-discharge studies of the solid-state PANI capacitors, a specific capacitance of 250 F g(-1) has been obtained at a specific power of 7.5 kW kg(-1) of PANI. The values of specific capacitance and specific power are considerably higher than those reported in the literature. High energy and high power characteristics of the PANI are presented. (C) 2002 The Electrochemical Society.