Irrevocabilidad Relajada para Memoria Transaccional Hardware

Los sistemas comerciales que ofrecen memoria transaccional (TM) implementan un sistema hardware best-effort (BE-HTM) con limitaciones. Es necesario programar un fallback software basado en cerrojos para asegurar el progreso de la aplicación. En este artículo se propone un nuevo tipo de irrevocabilidad hardware (un modo transaccional que marca las transacciones como no abortables) para hacer frente a las limitaciones de los sistemas BE-HTM de una manera mas eficiente, y para liberar a al usuario de tener que programar un fallback. Se basa en el concepto de suscripción relajada utilizada o en el contexto de la programación de fallbacks basada o en cerrojos, donde la transacción se suscribe al cerrojo al final de la misma en lugar de al principio. El mecanismo de irrevocabilidad relajada hardware no involucra cambios en el protocolo de coherencia y se compara con su homólogo software, que proponemos como un fallback con suscripción relajada de espera escapada. También proponemos la irrevocabilidad relajada con anticipación, un mecanismo que no se puede implementar en software, y que mejora el rendimiento de las aplicaciones con múltiples reemplazos de bloques transaccionales de caché. La evaluación de las propuestas se lleva a cabo con el simulador Simics/GEMS junto con la suite de benchmarks STAMP, y se obtiene una mejora de rendimiento sobre el fallback del 14% al 28% para algunos benchmarks.

MODELING AND HARDWARE-IN-THE-LOOP SIMULATION OF POWER-SPLIT HYBRID ELECTRIC VEHICLES

Conventional vehicles are creating pollution problems, global warming and the extinction of high density fuels. To address these problems, automotive companies and universities are researching on hybrid electric vehicles where two different power devices are used to propel a vehicle. This research studies the development and testing of a dynamic model for Prius 2010 Hybrid Synergy Drive (HSD), a power-split device. The device was modeled and integrated with a hybrid vehicle model. To add an electric only mode for vehicle propulsion, the hybrid synergy drive was modified by adding a clutch to carrier 1. The performance of the integrated vehicle model was tested with UDDS drive cycle using rule-based control strategy. The dSPACE Hardware-In-the-Loop (HIL) simulator was used for HIL simulation test. The HIL simulation result shows that the integration of developed HSD dynamic model with a hybrid vehicle model was successful. The HSD model was able to split power and isolate engine speed from vehicle speed in hybrid mode.

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Hardware processors for pairing-based cryptography

Bilinear pairings can be used to construct cryptographic systems with very desirable properties. A pairing performs a mapping on members of groups on elliptic and genus 2 hyperelliptic curves to an extension of the finite field on which the curves are defined. The finite fields must, however, be large to ensure adequate security. The complicated group structure of the curves and the expensive field operations result in time consuming computations that are an impediment to the practicality of pairing-based systems. The Tate pairing can be computed efficiently using the ɳT method. Hardware architectures can be used to accelerate the required operations by exploiting the parallelism inherent to the algorithmic and finite field calculations. The Tate pairing can be performed on elliptic curves of characteristic 2 and 3 and on genus 2 hyperelliptic curves of characteristic 2. Curve selection is dependent on several factors including desired computational speed, the area constraints of the target device and the required security level. In this thesis, custom hardware processors for the acceleration of the Tate pairing are presented and implemented on an FPGA. The underlying hardware architectures are designed with care to exploit available parallelism while ensuring resource efficiency. The characteristic 2 elliptic curve processor contains novel units that return a pairing result in a very low number of clock cycles. Despite the more complicated computational algorithm, the speed of the genus 2 processor is comparable. Pairing computation on each of these curves can be appealing in applications with various attributes. A flexible processor that can perform pairing computation on elliptic curves of characteristic 2 and 3 has also been designed. An integrated hardware/software design and verification environment has been developed. This system automates the procedures required for robust processor creation and enables the rapid provision of solutions for a wide range of cryptographic applications.

Towards a Multi-device Constraints Solver

To reduce the amount of time needed to solve the most complex Constraint Satisfaction Problems (CSPs) usually multi-core CPUs are used. There are already many applications capable of harnessing the parallel power of these devices to speed up the CSPs solving process. Nowadays, the Graphics Processing Units (GPUs) possess a level of parallelism that surpass the CPUs, containing from a few hundred to a few thousand cores and there are much less applications capable of solving CSPs on GPUs, leaving space for possible improvements. This article describes the work in progress for solving CSPs on GPUs and CPUs and compares results with some state-of-the-art solvers, presenting already some good results on GPUs.

Studio di un architettura hardware per il controllo di inverter per motori multifase

Lo scopo del lavoro è stato progettare una scheda di controllo in grado di concedere una buona flessibilità per il controllo di azionamenti elettrici, capace di interfacciarsi con configurazioni multi-livello, multifase e dual-motor. La progettazione è stata sviluppata con supporto di CAD elettronici commerciali. La scheda presenta tre parti fondamentali. Due unità di controllo identiche per permettere l’interfacciamento con più configurazioni, nelle quali sono realizzate tutte le funzioni di controllo, ed un’unità chiamata PL2 per la rielaborazione dati di tipologia unicamente automobilistica. E’ stato inoltre realizzato l’interfacciamento e l’assemblaggio con altre due schede elettroniche dedite all’attuazione dei segnali di controllo e alla gestione e rielaborazione dei segnali di veicolo.

Hardware-In-The Loop setup and test of an air spring control system

In this work, a Hardware-in-the-loop test bench is designed. The bench is used to test the behaviour of an electronic control unit used in Maserati to control the dynamics of an air spring system. First the mathematical model of the plant has been defined, then the simulation enviroment and the test environment have been set up. The performed tests succesfully highlighted some bugs in the device under test.

Hardware-in-the-loop implementation of single- and dual-phase shift control for dual active bridge converters in EV applications

Isolated DC-DC converters play a significant role in fast charging and maintaining the variable output voltage for EV applications. This study aims to investigate the different Isolated DC-DC converters for onboard and offboard chargers, then, once the topology is selected, study the control techniques and, finally, achieve a real-time converter model to accomplish Hardware-In-The-Loop (HIL) results. Among the different isolated DC-DC topologies, the Dual Active Bridge (DAB) converter has the advantage of allowing bidirectional power flow, which enables operating in both Grid to Vehicle (G2V) and Vehicle to Grid (V2G) modalities. Recently, DAB has been used in the offboard chargers for high voltage applications due to SiC and GaN MOSFETs; this new technology also allows the utilization of higher switching frequencies. By empowering soft switching techniques to reduce switching losses, higher switching frequency operation is possible in DAB. There are four phase shift control techniques for the DAB converter. They are Single Phase shift, Extended Phase shift, Dual Phase shift, Triple Phase shift controls. This thesis considers two control strategies; Single-Phase, and Dual-Phase shifts, to understand the circulating currents, power losses, and output capacitor size reduction in the DAB. Hardware-In-The-Loop (HIL) experiments are carried out on both controls with high switching frequencies using the PLECS software tool and the RT box supporting the PLECS. Root Mean Square Error is also calculated for steady-state values of output voltage with different sampling frequencies in both the controls to identify the achievable sampling frequency in real-time. DSP implementation is also executed to emulate the optimized DAB converter design, and final real-time simulation results are discussed for both the Single-Phase and Dual-Phase shift controls.

Hardware-software design of embedded systems for intelligent sensing applications

This Thesis wants to highlight the importance of ad-hoc designed and developed embedded systems in the implementation of intelligent sensor networks. As evidence four areas of application are presented: Precision Agriculture, Bioengineering, Automotive and Structural Health Monitoring. For each field is reported one, or more, smart device design and developing, in addition to on-board elaborations, experimental validation and in field tests. In particular, it is presented the design and development of a fruit meter. In the bioengineering field, three different projects are reported, detailing the architectures implemented and the validation tests conducted. Two prototype realizations of an inner temperature measurement system in electric motors for an automotive application are then discussed. Lastly, the HW/SW design of a Smart Sensor Network is analyzed: the network features on-board data management and processing, integration in an IoT toolchain, Wireless Sensor Network developments and an AI framework for vibration-based structural assessment.

The road to augmented reality: a comprehensive study of hardware and applications over the last ten years

Augmented reality has been growing extensively over the years in all aspects and multiple fields. My aim in this paper is to present a comprehensive study on augmented reality(AR) hardware and its applications from early developments to the possible future trends. Particularly my research is more focused on last 11 years(2012-2022), where I systematically reviewed 30 research papers per year to get a clear knowledge on trends of AR. A total of 330 publications were reviewed and grouped according to their application. The review's main contribution is to show the entire landscape of AR research and to provide a broad view of how it has evolved. Along with various AR glasses history and specifications are presented in detail. In the penultimate chapter I explained my methodology of research following my analysis from the past to the present along with my thoughts for the future. To conclude my study, In the final chapter I made some statements about possible future with AR, VR and XR(extended reality).

Studio di interazione hardware/software tra Raspberry e nanoVNA

L’obiettivo della tesi è quello di realizzare un progetto basato sull’interazione tra Raspberry Pi e NanoVNA, allo scopo di rendere automatico il processo di acquisizione dei dati di questo strumento di misura. A tal fine è stato sviluppato un programma in linguaggio Python, eseguibile dal terminale del Raspberry Pi, che permette all’utente di inserire agevolmente i parametri essenziali, come l’orario di inizio e termine delle misurazioni e l'intervallo di tempo tra una rilevazione e l’altra.

Nodi sensori LoRaWAN a micropotenze: progettazione hardware, firmware e a livello di applicazione

L'elaborato parte da una scheda di sviluppo commerciale per arrivare a realizzare una rete LoRaWAN comprensiva di End-Node, Gateway e Application Server. In maniera specifica, l'elaborato affronta il problema della progettazione di end-node a micropotenze. Dopo aver studiato e collaudato la piattaforma di sviluppo, è stata affrontata la problematica dell'ottimizzazione energetica a diversi livelli: scelta di componenti con correnti di perdita estremamente ridotte, tecniche di power gating temporizzato, comportamento adattativo del nodo, impostazione dei consumi del nodo mediante i server della rete. L'elaborato presenta infine il layout del PCB progettato, pronto per la fabbricazione, insieme a stime del tempo di vita dell'end-node in funzione della frequenza di trasmissione e della capacità delle batterie utilizzate.

Analysis, Design, and Hardware-in-the-Loop Validation of Multi-Active Bridge Converters

This master's thesis investigates different aspects of Dual-Active-Bridge (DAB) Converter and extends aspects further to Multi-Active-Bridges (MAB). The thesis starts with an overview of the applications of the DAB and MAB and their importance. The analytical part of the thesis includes the derivation of the peak and RMS currents, which is required for finding the losses present in the system. The power converters, considered in this thesis are DAB, Triple-Active Bridge (TAB) and Quad-Active Bridge (QAB). All the theoretical calculations are compared with the simulation results from PLECS software for identifying the correctness of the reviewed and developed theory. The Hardware-in-the-Loop (HIL) simulation is conducted for checking the control operation in real-time with the help of the RT box from the Plexim. Additionally, as in real systems digital signal processor (DSP), system-on-chip or field programmable gate array is employed for the control of the power electronic systems, and the execution of the control in the real-time simulation (RTS) conducted is performed by DSP.

Energy consumption of parallel algorithms for solving linear systems on HPC architecture

Modern High-Performance Computing HPC systems are gradually increasing in size and complexity due to the correspondent demand of larger simulations requiring more complicated tasks and higher accuracy. However, as side effects of the Dennard’s scaling approaching its ultimate power limit, the efficiency of software plays also an important role in increasing the overall performance of a computation. Tools to measure application performance in these increasingly complex environments provide insights into the intricate ways in which software and hardware interact. The monitoring of the power consumption in order to save energy is possible through processors interfaces like Intel Running Average Power Limit RAPL. Given the low level of these interfaces, they are often paired with an application-level tool like Performance Application Programming Interface PAPI. Since several problems in many heterogeneous fields can be represented as a complex linear system, an optimized and scalable linear system solver algorithm can decrease significantly the time spent to compute its resolution. One of the most widely used algorithms deployed for the resolution of large simulation is the Gaussian Elimination, which has its most popular implementation for HPC systems in the Scalable Linear Algebra PACKage ScaLAPACK library. However, another relevant algorithm, which is increasing in popularity in the academic field, is the Inhibition Method. This thesis compares the energy consumption of the Inhibition Method and Gaussian Elimination from ScaLAPACK to profile their execution during the resolution of linear systems above the HPC architecture offered by CINECA. Moreover, it also collates the energy and power values for different ranks, nodes, and sockets configurations. The monitoring tools employed to track the energy consumption of these algorithms are PAPI and RAPL, that will be integrated with the parallel execution of the algorithms managed with the Message Passing Interface MPI.

Analisi e studio computazionale di solver per problemi di routing di interesse industriale

Il Routing rappresenta uno dei problemi più studiati nell’ambito della Ricerca Operativa in quanto offre molteplici possibilità di ottimizzazione da cui possono derivare altrettanti vantaggi per le aziende che decidono di gestirlo in maniera strutturata. Uno dei principali ambiti di applicazione del routing è la pianificazione operativa del trasporto merci a clienti sparsi in un determinato territorio. Ci sono aziende che devono organizzare la loro Logistica distributiva ogni giorno. Ormai è diventato evidente che la realizzazione di questo processo mediante modalità “standard”, senza l’utilizzo di appositi strumenti di ottimizzazione, non solo porta alla perdita di occasioni importanti in termini di vantaggi raggiungibili, ma è anche molto più dispendiosa a livello di tempo richiesto. Molte aziende si stanno quindi affidando a soluzioni SW che si vadano ad integrare con i loro processi decisionali. Questi sistemi hanno alla base delle componenti algoritmiche in grado di trovare la migliore soluzione possibile per la tipologia specifica di Routing da affrontare. Per questi motivi, lo sviluppo di algoritmi in grado di risolvere questo problema rappresenta una parte consistente della letteratura scientifica in ambito di ottimizzazione. In questo elaborato si andranno a definire le principali caratteristiche di un problema di Routing in forma base e nelle sue varianti principali. Si descriveranno le caratteristiche dei problemi di Routing incontrati da Optit S.r.l, un’azienda che opera nel settore dello sviluppo di soluzioni SW di ottimizzazione. Nel fare ciò, si cercherà di trovare sovrapposizione con quanto descritto in letteratura. Infine, si descriveranno alcuni solver Open-Source per risolvere problemi di Routing e si mostreranno i risultati da essi ottenuti su alcuni casi di interesse industriale.