Burstlock : a digital phase-locked loop using burst techniques /

Thesis (M. S.)--University of Illinois at Urbana-Champaign.

Phase Locked Loop and Modulo Games, The Dogma Loops; and “Finding Ibrida”

This dissertation consists of two independent musical compositions and an article detailing the process of the design and assembly of an electric guitar with particular emphasis on the carefully curated suite of embedded effects.

The first piece, 'Phase Locked Loop and Modulo Games' is scored for electric guitar and a single echo of equal volume less than a beat away. One could think of the piece as a 15 minute canon at the unison at the dotted eighth note (or at times the quarter or triplet-quarter), however the compositional motivation is more about weaving a composite texture between the guitar and its echo that is, while in theory extremely contrapuntal, in actuality is simply a single [superhuman] melodic line.

The second piece, 'The Dogma Loops' picks up a few compositional threads left by ‘Phase Locked Loop’ and weaves them into an entirely new tapestry. 'Phase Locked Loop' is motivated by the creation of a complex musical composite that is for the most part electronically transparent. 'The Dogma Loops' questions that same notion of composite electronic complexity by essentially asking a question: "what are the inputs to an interactive electronic system that create the most complex outputs via the simplest musical means possible?"

'The Dogma Loops' is scored for Electric Guitar (doubling on Ukulele), Violin and Violoncello. All of the principal instruments require an electronic pickup (except the Uke). The work is in three sections played attacca; [Automation Games], [Point of Origin] and [Cloning Vectors].

The third and final component of the document is the article 'Finding Ibrida.' This article details the process of the design and assembly of an electric guitar with integrated effects, while also providing the deeper context (conceptual and technical) which motivated the efforts and informed the challenges to hybridize the various technologies (tubes, transistors, digital effects and a microcontroller subsystem). The project was motivated by a desire for rigorous technical and hands-on engagement with analog signal processing as applied to the electric guitar. ‘Finding Ibrida’ explores sound, some myths and lore of guitar tech and the history of electric guitar distortion and its culture of sonic exploration.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

Injection Locked Clocking and Transmitter Equalization Techniques for Chip to Chip Interconnects

Semiconductor technology scaling has enabled drastic growth in the computational capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high bandwidth communication between ICs. Electrical channel bandwidth has not been able to keep up with this demand, making I/O link design more challenging. Interconnects which employ optical channels have negligible frequency dependent loss and provide a potential solution to this I/O bandwidth problem. Apart from the type of channel, efficient high-speed communication also relies on generation and distribution of multi-phase, high-speed, and high-quality clock signals. In the multi-gigahertz frequency range, conventional clocking techniques have encountered several design challenges in terms of power consumption, skew and jitter. Injection-locking is a promising technique to address these design challenges for gigahertz clocking. However, its small locking range has been a major contributor in preventing its ubiquitous acceptance.

In the first part of this dissertation we describe a wideband injection locking scheme in an LC oscillator. Phase locked loop (PLL) and injection locking elements are combined symbiotically to achieve wide locking range while retaining the simplicity of the latter. This method does not require a phase frequency detector or a loop filter to achieve phase lock. A mathematical analysis of the system is presented and the expression for new locking range is derived. A locking range of 13.4 GHz–17.2 GHz (25%) and an average jitter tracking bandwidth of up to 400 MHz are measured in a high-Q LC oscillator. This architecture is used to generate quadrature phases from a single clock without any frequency division. It also provides high frequency jitter filtering while retaining the low frequency correlated jitter essential for forwarded clock receivers.

To improve the locking range of an injection locked ring oscillator; QLL (Quadrature locked loop) is introduced. The inherent dynamics of injection locked quadrature ring oscillator are used to improve its locking range from 5% (7-7.4GHz) to 90% (4-11GHz). The QLL is used to generate accurate clock phases for a four channel optical receiver using a forwarded clock at quarter-rate. The QLL drives an injection locked oscillator (ILO) at each channel without any repeaters for local quadrature clock generation. Each local ILO has deskew capability for phase alignment. The optical-receiver uses the inherent frequency to voltage conversion provided by the QLL to dynamically body bias its devices. A wide locking range of the QLL helps to achieve a reliable data-rate of 16-32Gb/s and adaptive body biasing aids in maintaining an ultra-low power consumption of 153pJ/bit.

From the optical receiver we move on to discussing a non-linear equalization technique for a vertical-cavity surface-emitting laser (VCSEL) based optical transmitter, to enable low-power, high-speed optical transmission. A non-linear time domain optical model of the VCSEL is built and evaluated for accuracy. The modelling shows that, while conventional FIR-based pre-emphasis works well for LTI electrical channels, it is not optimum for the non-linear optical frequency response of the VCSEL. Based on the simulations of the model an optimum equalization methodology is derived. The equalization technique is used to achieve a data-rate of 20Gb/s with power efficiency of 0.77pJ/bit.

Modulation Insensitive PLL for Tracking Antenna Applications

This article shows practical results of a self-tracking receiving antenna array using a new phase locked loop (PLL) tracking configuration. The PLL configuration differs from other architectures, as it has the new feature of being able to directly track phase modulated signals without requiring an additional unmodulated pilot carrier to be present. The PLLs are used within the antenna array to produce a constant phase intermediate frequency (IF) for each antenna element. These IF's can then be combined in phase, regardless of the angle of arrival of the signal, thus utilizing the antennas array factor. The article's main focus is on the phase jitter performance of the modulation insensitive PLL carrier recovery when tracking phase modulated signals of low signal to noise ratio. From this analysis, it is concluded that the new architecture, when optimally designed, can produce phase jitter performance close to that of a conventional tracking PLL.

Quadrature-phase noise penalties of optically and electro-optically phase-locked lasers

Focussing particularly on solid-state laser systems, the phase-noise penalties of laser injection-locking and electro-optical phase-locking are derived using linearised quantum mechanical models. The fundamental performance limit (minimum achievable output phase noise) for an injection-locked laser (IJL) system at low frequencies is equal to that of a standard phase-insensitive amplifier, whereas, in principle, that of a phase-locked laser (PLL) system can be better. At high frequencies, the output phase noise of the IJL system is limited by that of the master laser, while that of the PLL system tends to a weighted sum of contributions from the master and slave laser fields. Under conditions of large amplification, particularly where there has been significant attenuation, the noise penalties are shown to be substantial. Nonideal photodetector characteristics are shown to add significantly to the noise penalties for the PLL system. (C) 2005 Elsevier B.V. All rights reserved.

Development of innovative robust stability enhancement algorithms for distribution systems containing distributed generators

This project was a step forward in improving the voltage profile of traditional low voltage distribution networks with high photovoltaic generation or high peak demand. As a practical and economical solution, the developed methods use a Dynamic Voltage Restorer or DVR, which is a series voltage compensator, for continuous and communication-less power quality enhancement. The placement of DVR in the network is optimised in order to minimise its power rating and cost. In addition, new approaches were developed for grid synchronisation and control of DVR which are integrated with the voltage quality improvement algorithm for stable operation.

Timing Recovery Algorithms and Architectures for 2-D Magnetic Recording Systems

We investigate the problem of timing recovery for 2-D magnetic recording (TDMR) channels. We develop a timing error model for TDMR channel considering the phase and frequency offsets with noise. We propose a 2-D data-aided phase-locked loop (PLL) architecture for tracking variations in the position and movement of the read head in the down-track and cross-track directions and analyze the convergence of the algorithm under non-separable timing errors. We further develop a 2-D interpolation-based timing recovery scheme that works in conjunction with the 2-D PLL. We quantify the efficiency of our proposed algorithms by simulations over a 2-D magnetic recording channel with timing errors.

Detecção e classificação de VTCDs em sistemas de distribuição de energia elétrica usando redes neurais artificiais.

O objetivo deste trabalho é conhecer e compreender melhor os imprevistos no fornecimento de energia elétrica, quando ocorrem as variações de tensão de curta duração (VTCD). O banco de dados necessário para os diagnósticos das faltas foi obtido através de simulações de um modelo de alimentador radial através do software PSCAD/EMTDC. Este trabalho utiliza um Phase-Locked Loop (PLL) com o intuito de detectar VTCDs e realizar a estimativa automática da frequência, do ângulo de fase e da amplitude das tensões e correntes da rede elétrica. Nesta pesquisa, desenvolveram-se duas redes neurais artificiais: uma para identificar e outra para localizar as VTCDs ocorridas no sistema de distribuição de energia elétrica. A técnica aqui proposta aplica-se a alimentadores trifásicos com cargas desequilibradas, que podem possuir ramais laterais trifásicos, bifásicos e monofásicos. No desenvolvimento da mesma, considera-se que há disponibilidade de medições de tensões e correntes no nó inicial do alimentador e também em alguns pontos esparsos ao longo do alimentador de distribuição. Os desempenhos das arquiteturas das redes neurais foram satisfatórios e demonstram a viabilidade das RNAs na obtenção das generalizações que habilitam o sistema para realizar a classificação de curtos-circuitos.

Localização de faltas de curta duração em redes de distribuição.

O objetivo deste trabalho é contribuir com o desenvolvimento de uma técnica baseada em sistemas inteligentes que possibilite a localização exata ou aproximada do ponto de origem de uma Variação de Tensão de Curta Duração (VTCD) (gerada por uma falta) em um sistema de distribuição de energia elétrica. Este trabalho utiliza um Phase-Locked Loop (PLL) com o intuito de detectar as faltas. Uma vez que a falta é detectada, os sinais de tensão obtidos durante a falta são decompostos em componentes simétricas instantâneas por meio do método proposto. Em seguida, as energias das componentes simétricas são calculadas e utilizadas para estimar a localização da falta. Nesta pesquisa, são avaliadas duas estruturas baseadas em Redes Neurais Artificiais (RNAs). A primeira é projetada para classificar a localização da falta em um dos pontos possíveis e a segunda é projetada para estimar a distância da falta ao alimentador. A técnica aqui proposta aplica-se a alimentadores trifásicos com cargas equilibradas. No desenvolvimento da mesma, considera-se que há disponibilidade de medições de tensões no nó inicial do alimentador e também em pontos esparsos ao longo da rede de distribuição. O banco de dados empregado foi obtido através de simulações de um modelo de alimentador radial usando o programa PSCAD/EMTDC. Testes de sensibilidade empregando validação-cruzada são realizados em ambas as arquiteturas de redes neurais com o intuito de verificar a confiabilidade dos resultados obtidos. Adicionalmente foram realizados testes com faltas não inicialmente contidas no banco de dados a fim de se verificar a capacidade de generalização das redes. Os desempenhos de ambas as arquiteturas de redes neurais foram satisfatórios e demonstram a viabilidade das técnicas propostas para realizar a localização de faltas em redes de distribuição.

An adaptive frequency synthesizer architecture reducing reference sidebands

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18um CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.

Análise e implementação digital de uma malha de captura de fase para sincronização de conversores à rede elétrica

Dissertação para a obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Eletrónica Industrial

Controle Adaptativo Robusto para Filtros Ativos de Potência Paralelo

Conventional control strategies used in shunt active power filters (SAPF) employs real-time instantaneous harmonic detection schemes which is usually implements with digital filters. This increase the number of current sensors on the filter structure which results in high costs. Furthermore, these detection schemes introduce time delays which can deteriorate the harmonic compensation performance. Differently from the conventional control schemes, this paper proposes a non-standard control strategy which indirectly regulates the phase currents of the power mains. The reference currents of system are generated by the dc-link voltage controller and is based on the active power balance of SAPF system. The reference currents are aligned to the phase angle of the power mains voltage vector which is obtained by using a dq phase locked loop (PLL) system. The current control strategy is implemented by an adaptive pole placement control strategy integrated to a variable structure control scheme (VS-APPC). In the VS-APPC, the internal model principle (IMP) of reference currents is used for achieving the zero steady state tracking error of the power system currents. This forces the phase current of the system mains to be sinusoidal with low harmonics content. Moreover, the current controllers are implemented on the stationary reference frame to avoid transformations to the mains voltage vector reference coordinates. This proposed current control strategy enhance the performance of SAPF with fast transient response and robustness to parametric uncertainties. Experimental results are showing for determining the effectiveness of SAPF proposed control system

Estratégia de controle robusto para filtro ativo paralelo sem detecção de harmônicos de correntes

Conventional control strategies used in shunt active power filters (SAPF) employs real-time instantaneous harmonic detection schemes which is usually implements with digital filters. This increase the number of current sensors on the filter structure which results in high costs. Furthermore, these detection schemes introduce time delays which can deteriorate the harmonic compensation performance. Differently from the conventional control schemes, this paper proposes a non-standard control strategy which indirectly regulates the phase currents of the power mains. The reference currents of system are generated by the dc-link voltage controller and is based on the active power balance of SAPF system. The reference currents are aligned to the phase angle of the power mains voltage vector which is obtained by using a dq phase locked loop (PLL) system. The current control strategy is implemented by an adaptive pole placement control strategy integrated to a variable structure control scheme (VS¡APPC). In the VS¡APPC, the internal model principle (IMP) of reference currents is used for achieving the zero steady state tracking error of the power system currents. This forces the phase current of the system mains to be sinusoidal with low harmonics content. Moreover, the current controllers are implemented on the stationary reference frame to avoid transformations to the mains voltage vector reference coordinates. This proposed current control strategy enhance the performance of SAPF with fast transient response and robustness to parametric uncertainties. Experimental results are showing for determining the effectiveness of SAPF proposed control system

Simulations of the Frequency Modulated Atomic Force Microscope (FM-AFM) nonlinear control system

The Frequency Modulated - Atomic Force Microscope (FM-AFM) is apowerful tool to perform surface investigation with true atomic resolution. The controlsystem of the FM-AFM must keep constant both the frequency and amplitude ofoscillation of the microcantilever during the scanning process of the sample. However,tip and sample interaction forces cause modulations in the microcantilever motion.A Phase-Locked Loop (PLL) is used as a demodulator and to generate feedback signalto the FM-AFM control system. The PLL performance is vital to the FM-AFMperformace since the image information is in the modulated microcantilever motion.Nevertheless, little attention is drawn to PLL performance in the FM-AFM literature.Here, the FM-AFM control system is simulated, comparing the performancefor di erent PLL designs.