Aplicació Web SONIN (Sistema Orientatiu Intel ligent)

L¿objectiu és un obtenir una aplicació per al control i homologació de les dades introduïdes pels usuaris en el e-CAP/SIAP (aplicacions informàtiques que gestionen l'activitat sanitària de la primària a Barcelona).Així que desenvoluparem una aplicació web amb eines de programació de Microsoft per facilitar la tasca principalment del personal auxiliar administratiu dels a l'hora de decidir el contingut de determinats valors a introduir en el e-CAP/SIAP.

An embedded real-time red peach detection system based on an OV7670 camera, ARM Cortex-M4 processor and 3D Look-Up Tables

This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6) processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future robotized harvesting arm. The embedded system will be able to perform real-time fruit detection and tracking by using a three-dimensional look-up-table (LUT) defined in the RGB color space and optimized for fruit picking. Additionally, two different methodologies for creating optimized 3D LUTs based on existing linear color models and fruit histograms were implemented in this work and compared for the case of red peaches. The resulting system is able to acquire general and zoomed orchard images and to update the relative tracking information of a red peach in the tree ten times per second.

Tuning Performance of Multi-threaded programs

Diplomityö tarkastelee säikeistettyä ohjelmointia rinnakkaisohjelmoinnin ylemmällä hierarkiatasolla tarkastellen erityisesti hypersäikeistysteknologiaa. Työssä tarkastellaan hypersäikeistyksen hyviä ja huonoja puolia sekä sen vaikutuksia rinnakkaisalgoritmeihin. Työn tavoitteena oli ymmärtää Intel Pentium 4 prosessorin hypersäikeistyksen toteutus ja mahdollistaa sen hyödyntäminen, missä se tuo suorituskyvyllistä etua. Työssä kerättiin ja analysoitiin suorituskykytietoa ajamalla suuri joukko suorituskykytestejä eri olosuhteissa (muistin käsittely, kääntäjän asetukset, ympäristömuuttujat...). Työssä tarkasteltiin kahdentyyppisiä algoritmeja: matriisioperaatioita ja lajittelua. Näissä sovelluksissa on säännöllinen muistinkäyttökuvio, mikä on kaksiteräinen miekka. Se on etu aritmeettis-loogisissa prosessoinnissa, mutta toisaalta huonontaa muistin suorituskykyä. Syynä siihen on nykyaikaisten prosessorien erittäin hyvä raaka suorituskyky säännöllistä dataa käsiteltäessä, mutta muistiarkkitehtuuria rajoittaa välimuistien koko ja useat puskurit. Kun ongelman koko ylittää tietyn rajan, todellinen suorituskyky voi pudota murto-osaan huippusuorituskyvystä.

A System-Level Simulation Model for a Protocol Processor

As the development of integrated circuit technology continues to follow Moore’s law the complexity of circuits increases exponentially. Traditional hardware description languages such as VHDL and Verilog are no longer powerful enough to cope with this level of complexity and do not provide facilities for hardware/software codesign. Languages such as SystemC are intended to solve these problems by combining the powerful expression of high level programming languages and hardware oriented facilities of hardware description languages. To fully replace older languages in the desing flow of digital systems SystemC should also be synthesizable. The devices required by modern high speed networks often share the same tight constraints for e.g. size, power consumption and price with embedded systems but have also very demanding real time and quality of service requirements that are difficult to satisfy with general purpose processors. Dedicated hardware blocks of an application specific instruction set processor are one way to combine fast processing speed, energy efficiency, flexibility and relatively low time-to-market. Common features can be identified in the network processing domain making it possible to develop specialized but configurable processor architectures. One such architecture is the TACO which is based on transport triggered architecture. The architecture offers a high degree of parallelism and modularity and greatly simplified instruction decoding. For this M.Sc.(Tech) thesis, a simulation environment for the TACO architecture was developed with SystemC 2.2 using an old version written with SystemC 1.0 as a starting point. The environment enables rapid design space exploration by providing facilities for hw/sw codesign and simulation and an extendable library of automatically configured reusable hardware blocks. Other topics that are covered are the differences between SystemC 1.0 and 2.2 from the viewpoint of hardware modeling, and compilation of a SystemC model into synthesizable VHDL with Celoxica Agility SystemC Compiler. A simulation model for a processor for TCP/IP packet validation was designed and tested as a test case for the environment.

Ús del Capital Social i la Intel.ligència Competitiva per part de les Universitats en el procés d"adaptació a l"EEES

En la present comunicació s'exposen els resultats del projecte ¿Análisis de los procedimientos de interacción entorno-universidad en el proceso de adaptación e implementación de titulaciones oficiales al EEES" finançat pel Ministerio de Ciencia e Innovación, en la convocatòria d'Estudios y Anàlisis, 2008. Un dels objectius d'aquest projecte era conèixer, de forma exploratòria, quines eines havien emprat lesUniversitats per tal d'adaptar les seves titulacions al nou EEES, considerant diversosfactors. Entre aquests, l'ús del Capital Social del qual disposen les Universitats, entès tant de d¿una òptica interna com externa. A la vegada, es pretenia analitzar si la Universitat disposa de veritables eines d'Intel·ligència Competitiva per tal d'interpretar adequadament el seu entorn. D'entre diverses conclusions, s'extreu que les Universitats no aprofiten suficientment els contactes que generen amb el seu entorn per tal de potenciar la seva competitivitat i les noves titulacions adaptades a l'EEES.

A Co-Processor Approach for Efficient Java Execution in Embedded Systems

This thesis deals with a hardware accelerated Java virtual machine, named REALJava. The REALJava virtual machine is targeted for resource constrained embedded systems. The goal is to attain increased computational performance with reduced power consumption. While these objectives are often seen as trade-offs, in this context both of them can be attained simultaneously by using dedicated hardware. The target level of the computational performance of the REALJava virtual machine is initially set to be as fast as the currently available full custom ASIC Java processors. As a secondary goal all of the components of the virtual machine are designed so that the resulting system can be scaled to support multiple co-processor cores. The virtual machine is designed using the hardware/software co-design paradigm. The partitioning between the two domains is flexible, allowing customizations to the resulting system, for instance the floating point support can be omitted from the hardware in order to decrease the size of the co-processor core. The communication between the hardware and the software domains is encapsulated into modules. This allows the REALJava virtual machine to be easily integrated into any system, simply by redesigning the communication modules. Besides the virtual machine and the related co-processor architecture, several performance enhancing techniques are presented. These include techniques related to instruction folding, stack handling, method invocation, constant loading and control in time domain. The REALJava virtual machine is prototyped using three different FPGA platforms. The original pipeline structure is modified to suit the FPGA environment. The performance of the resulting Java virtual machine is evaluated against existing Java solutions in the embedded systems field. The results show that the goals are attained, both in terms of computational performance and power consumption. Especially the computational performance is evaluated thoroughly, and the results show that the REALJava is more than twice as fast as the fastest full custom ASIC Java processor. In addition to standard Java virtual machine benchmarks, several new Java applications are designed to both verify the results and broaden the spectrum of the tests.

Patentointiaktiivisuuden muutos x86-prosessorivalmistajien keskuudessa vuosina 1985-2009 Case: Intel

Työssä tutkitaan x86-prosessorivalmistajien patentointiaktiivisuuden muutosta vuosina 1985 – 2009 Intelin kautta. Työn tavoitteena on selvittää syitä, jotka ovat johtaneet patentointiaktiivisuuden radikaaliin muutokseen toimialalla. Työssä esitellään patenttien tärkeys teknologiayrityksille ja miten patentointiaktiivisuus on muuttunut x86-prosessorivalmistajien keskuudessa. Työssä käsitellään patenttiteoriaa, esimerkiksi patenttijärjestelmää ja yrityksen patenttipolitiikkaa. Työssä käsitellään ei-valmistavia patenttitaloja ja luodaan katsaus niiden vaikutuksiin valmistaville yrityksille. Tämän jälkeen perehdytään yksityiskohtaisemmin teknologiajätti Inteliin. Työn tarkoitus on selvittää, onko toimialan patentointiaktiivisuus hidastumassa tai pysähtynyt. Työssä pyritään löytämään mahdollisia syitä Intelin patentointiaktiivisuuden muutokseen.

SCIL processor : a common intermediate language processor for embedded systems

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

A Concurrent Smalltalk Compiler for the Message-Driven Processor

This thesis describes Optimist, an optimizing compiler for the Concurrent Smalltalk language developed by the Concurrent VLSI Architecture Group. Optimist compiles Concurrent Smalltalk to the assembly language of the Message-Driven Processor (MDP). The compiler includes numerous optimization techniques such as dead code elimination, dataflow analysis, constant folding, move elimination, concurrency analysis, duplicate code merging, tail forwarding, use of register variables, as well as various MDP-specific optimizations in the code generator. The MDP presents some unique challenges and opportunities for compilation. Due to the MDP's small memory size, it is critical that the size of the generated code be as small as possible. The MDP is an inherently concurrent processor with efficient mechanisms for sending and receiving messages; the compiler takes advantage of these mechanisms. The MDP's tagged architecture allows very efficient support of object-oriented languages such as Concurrent Smalltalk. The initial goals for the MDP were to have the MDP execute about twenty instructions per method and contain 4096 words of memory. This compiler shows that these goals are too optimistic -- most methods are longer, both in terms of code size and running time. Thus, the memory size of the MDP should be increased.

Concurrent Smalltalk on the Message-Driven Processor

Concurrent Smalltalk is the primary language used for programming the J- Machine, a MIMD message-passing computer containing thousands of 36-bit processors connected by a very low latency network. This thesis describes in detail Concurrent Smalltalk and its implementation on the J-Machine, including the Optimist II global optimizing compiler and Cosmos fine-grain parallel operating system. Quantitative and qualitative results are presented.

Cervell, intel.ligències i dissenys d'ensenyament-aprenentatge. 'Cerebro, inteligencias y diseños de enseñanza-aprendizaje'

Se expone la diversidad de estilos cognitivos y de estilos de aprendizaje producto de los factores dominantes del funcionamiento del cerebro. El repaso, breve pero conciso, hace un recorrido por las partes del cerebro más desarrolladas en cuanto al aprendizaje se refiere. También proporciona pautas y metodologías de actuación en el aula para mejorar la enseñanza en el día a día, partiendo de una motivación y una emoción que los maestros deben transmitir a sus alumnos para obtener buenos resultados, tanto cognitivos como del propio desarrollo personal .

Avaluació de la intel.ligència a partir de tests de relacions lògiques. 'Evaluación de la inteligencia a partir de tests de relaciones lógicas'.

Crear dos tests de inteligencia basados en relaciones lógicas y evaluar su aplicación.. 60 niños de edades entre 13-14 años de escuelas públicas.. Realiza un análisis histórico y evolutivo del concepto inteligencia y conceptos relacionados (modelos, estructuras jerarquicas, procesos intelecturales, conducta, metacognición, estrategias de aprendizaje). Elabora dos test de inteligencia: el TRL-LI (test de relaciones lógicas con letras) y el TRL-F (test de relaciones lógicas con figuras). Depura estos dos instrumentos y realiza un estudio práctico donde se contrastan los dos tests. Factores analizados: razonamiento abstracto general, razonamiento abstracto a partir del AMPE, relaciones lógicas entre conjuntos y relaciones lógicas en complemento de estructuras complejas no verbales.. Test ad-hoc, RAVEN D-48, DAT-AR, PMA-R1, PMA-R3, AMPE-R1, AMPE-R3 . Medias, desviaciones standars, varianza, índice de Cronbach, cargas factoriales (rotación varimax). . Presenta una tabla resumen de los resultados en cargas factoriales (rotación varimax) y varianza justificada en tantos por ciento de la aplicación de cada test que se correponde al análisis de lso cuatro factores analizados. . El factor de razonamiento abstracto general se puede identificar mediante los test DOMINO D-48, DAT-AR, PMA-R1 y PMA-R3. Relaciones lógicas entre conjuntos es un factor que se puede identificar mediante los tests: TRS-L1 y el TRL-F. El TRL-L1 mide las relaciones lógicas a partir de símbolos verbales y letras. El TRL-F mide las relaciones lógicas a partir de figuras..

Per un consum racional i una utilitzaci?? intel??ligent de les pantalles

Resumen basado en el de la publicaci??n