Performance analysis of boron nitride embedded armchair graphene nanoribbon metal-oxide-semiconductor field effect transistor with Stone Wales defects

We study the performance of a hybrid Graphene-Boron Nitride armchair nanoribbon (a-GNR-BN) n-MOSFET at its ballistic transport limit. We consider three geometric configurations 3p, 3p + 1, and 3p + 2 of a-GNR-BN with BN atoms embedded on either side (2, 4, and 6 BN) on the GNR. Material properties like band gap, effective mass, and density of states of these H-passivated structures are evaluated using the Density Functional Theory. Using these material parameters, self-consistent Poisson-Schrodinger simulations are carried out under the Non Equilibrium Green's Function formalism to calculate the ballistic n-MOSFET device characteristics. For a hybrid nanoribbon of width similar to 5 nm, the simulated ON current is found to be in the range of 265 mu A-280 mu A with an ON/OFF ratio 7.1 x 10(6)-7.4 x 10(6) for a V-DD = 0.68 V corresponding to 10 nm technology node. We further study the impact of randomly distributed Stone Wales (SW) defects in these hybrid structures and only 2.5% degradation of ON current is observed for SW defect density of 3.18%. (C) 2014 AIP Publishing LLC.

Trapped charge dynamics in a sol-gel based TiO(2) high- k gate dielectric silicon metal-oxide-semiconductor field effect transistor.

We have studied the response of a sol-gel based TiO(2), high k dielectric field effect transistor structure to microwave radiation. Under fixed bias conditions the transistor shows frequency dependent current fluctuations when exposed to continuous wave microwave radiation. Some of these fluctuations take the form of high Q resonances. The time dependent characteristics of these responses were studied by modulating the microwaves with a pulse signal. The measurements show that there is a shift in the centre frequency of these high Q resonances when the pulse time is varied. The measured lifetime of these resonances is high enough to be useful for non-classical information processing.

Amorphous silicon thin film transistor biosensing system

Electronic systems are a very good platform for sensing biological signals for fast point-of-care diagnostics or threat detection. One of the solutions is the lab-on-a-chip integrated circuit (IC), which is low cost and high reliability, offering the possibility for label-free detection. In recent years, similar integrated biosensors based on the conventional complementary metal oxide semiconductor (CMOS) technology have been reported. However, post-fabrication processes are essential for all classes of CMOS biochips, requiring biocompatible electrode deposition and circuit encapsulation. In this work, we present an amorphous silicon (a-Si) thin film transistor (TFT) array based sensing approach, which greatly simplifies the fabrication procedures and even decreases the cost of the biosensor. The device contains several identical sensor pixels with amplifiers to boost the sensitivity. Ring oscillator and logic circuits are also integrated to achieve different measurement methodologies, including electro-analytical methods such as amperometric and cyclic voltammetric modes. The system also supports different operational modes. For example, depending on the required detection arrangement, a sample droplet could be placed on the sensing pads or the device could be immersed into the sample solution for real time in-situ measurement. The entire system is designed and fabricated using a low temperature TFT process that is compatible to plastic substrates. No additional processing is required prior to biological measurement. A Cr/Au double layer is used for the biological-electronic interface. The success of the TFT-based system used in this work will open new avenues for flexible label-free or low-cost disposable biosensors. © 2013 Materials Research Society.

Multiple valley couplings in nanometer Si metal-oxide-semiconductor field-effect transistors

We investigate the couplings between different energy band valleys in a metal-oxide-semiconductor field-effect transistor (MOSFET) device using self-consistent calculations of million-atom Schrodinger-Poisson equations. Atomistic empirical pseudopotentials are used to describe the device Hamiltonian and the underlying bulk band structure. The MOSFET device is under nonequilibrium condition with a source-drain bias up to 2 V and a gate potential close to the threshold potential. We find that all the intervalley couplings are small, with the coupling constants less than 3 meV. As a result, the system eigenstates derived from different bulk valleys can be calculated separately. This will significantly reduce the simulation time because the diagonalization of the Hamiltonian matrix scales as the third power of the total number of basis functions. (C) 2008 American Institute of Physics.

Quantum mechanical simulation of nanosized metal-oxide-semiconductor field-effect transistor using empirical pseudopotentials: A comparison for charge density occupation methods

The atomistic pseudopotential quantum mechanical calculations are used to study the transport in million atom nanosized metal-oxide-semiconductor field-effect transistors. In the charge self-consistent calculation, the quantum mechanical eigenstates of closed systems instead of scattering states of open systems are calculated. The question of how to use these eigenstates to simulate a nonequilibrium system, and how to calculate the electric currents, is addressed. Two methods to occupy the electron eigenstates to yield the charge density in a nonequilibrium condition are tested and compared. One is a partition method and another is a quasi-Fermi level method. Two methods are also used to evaluate the current: one uses the ballistic and tunneling current approximation, another uses the drift-diffusion method. (C) 2009 American Institute of Physics. [doi:10.1063/1.3248262]

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

Transfer and detection of single electrons using metal-oxide-semiconductor field-effect transistors

A single-electron turnstile and electrometer circuit was fabricated on a silicon-on-insulator substrate. The turnstile, which is operated by opening and closing two metal-oxide-semiconductor field-effect transistors (MOSFETs) alternately, allows current quantization at 20 K due to single-electron transfer. Another MOSFET is placed at the drain side of the turnstile to form an electron storage island. Therefore, one-by-one electron entrance into the storage island from the turnstile can be detected as an abrupt change in the current of the electrometer, which is placed near the storage island and electrically coupled to it. The correspondence between the quantized current and the single-electron counting was confirmed.

Silicon light emitting devices in CMOS technology

Two silicon light emitting devices with different structures are realized in standard 0.35 mu m complementary metal-oxide-semiconductor (CMOS) technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6 nW and 12.1 nW are measured at 10 V and 100 mA, respectively, and both the calculated light emission intensities are more than 1 mW/Cm-2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm..

A 1Gb/s silicon photo-receiver in standard CMOS for 850-nm optical communication

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.