RBF circuits based on folded cascode differential pairs

We propose new circuits for the implementation of Radial Basis Functions such as Gaussian and Gaussian-like functions. These RBFs are obtained by the subtraction of two differential pair output currents in a folded cascode configuration. We also propose a multidimensional version based on the unidimensional circuits. SPICE simulation results indicate good functionality. These circuits are intended to be applied in the implementation of radial basis function networks. One possible application of these networks is transducer signal conditioning in aircraft and spacecraft vehicles onboard telemetry systems. Copyright 2008 ACM.

Radial basis function circuits using folded cascode differential pairs

In this paper, we propose new circuits for the implementation of Radial Basis Functions (RBF). These RBFs are obtained by the subtraction of two differential pair output currents in a folded cascode configuration. We also propose a multidimensional version based on the unidimensional circuits. SPICE simulation and experimental results indicate good functionality. These circuits are intended to be applied in the implementation of radial basis function networks. Possible applications of these networks include transducer signal conditioning and processing in onboard telemetry systems for aircraft and spacecraft vehicles. © 2010 IEEE.

Automated power semiconductor switching performance feature extraction from experimental double-pulse waveform data

Double-pulse tests are commonly used as a method for assessing the switching performance of power semiconductor switches in a clamped inductive switching application. Data generated from these tests are typically in the form of sampled waveform data captured using an oscilloscope. In cases where it is of interest to explore a multi-dimensional parameter space and corresponding result space it is necessary to reduce the data into key performance metrics via feature extraction. This paper presents techniques for the extraction of switching performance metrics from sampled double-pulse waveform data. The reported techniques are applied to experimental data from characterisation of a cascode gate drive circuit applied to power MOSFETs.

Comparative switching behaviour of silicon transistors and practical silicon carbide transistors

The motivation for our work is to identify a space for silicon carbide (SiC) devices in the silicon (Si) world. This paper presents a detailed experimental investigation of the switching behaviour of silicon and silicon carbide transistors (a JFET and a cascode device comprising a Si-MOSFET and a SiC-JFET). The experimental method is based on a clamped inductive load chopper circuit that puts considerable stress on the device and increases the transient power dissipation. A precise comparison of switching behaviour of Si and SiC devices on similar terms is the novelty of our work. The cascode is found to be an attractive fast switching device, capable of operating in two different configurations whose switching equivalent circuits are proposed here. The effect of limited dv/dt of the Si-MOSFET on the switching of the SiC-JFET in a cascode is also critically analysed.

Parameter extraction and calorimetric validation for a silicon carbide jfet pspice model

This paper focuses on the PSpice model of SiC-JFET element inside a SiCED cascode device. The device model parameters are extracted from the I-V and C-V characterization curves. In order to validate the model, an inductive test rig circuit is designed and tested. The switching loss is estimated both using oscilloscope and calorimeter. These results are found to be in good agreement with the simulated results.

A 1Gb/s silicon photo-receiver in standard CMOS for 850-nm optical communication

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.

A CMOS front-end circuit for SONET OC-96 receiver

An optical receiver front-end for SONET OC-96 receivers was analyzed and designed in 0.18 mu m CMOS process. It consists of a transimpedance amplifier (TIA) and a limiting amplifier (LA). The TIA takes a fully differential configuration, and regulated cascode (RGC) input stage is implemented. The LA was realized by five cascaded identical gain stages with active inductor load. The TIA achieved 4.2GHz bandwidth for 0.5pF photodiode (PD) capacitance and 1.2k 0 transimpedance gain. The LA achieved 5.4GHz bandwidth and 29dB voltage gain. The optical sensitivity is -19dBm at 5-Gb/s for a bit-error rate of 10(-12), and it dissipates 45.5mW for I.8V supply.

一种红外探测器专用77K工作CMOS前置放大器

利用single endedfolded cascode结构和MOS管工作在线性区做反馈电阻,实现了一种在77K工作的高性能低功耗、低噪声前置放大器.分析了它的噪声特性,提出了减少噪声的措施.此前置放大器用1.2μm的标准CMOS工艺制造完成.经过测试,这种前置放大器在低温77K下能正常工作,反馈电阻大小为兆欧级,线性度达到了1%,等效输入噪声电流仅0.03pA/Hz,功耗小于1mW.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

A 76-84 GHz SiGe power amplifier array employing low-loss four-way differential combining transformer

This paper presents holistic design of a novel four-way differential power-combining transformer for use in millimeter-wave power-amplifier (PA). The combiner with an inner radius of 25 µm exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. It is designed to simultaneously act as a balanced-to-unbalanced converter, removing the need for additional BALUNs typically required in differential circuits. A complete circuit comprised of a power splitter, two-stage differential cascode PA array, a power combiner as well as input and output matching elements was designed and realized in SiGe technology with f/f 170/250 GHz. Measured small-signal gain of at least 16.8 dB was obtained from 76.4 to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm output referred 1 dB compression point and 14 dBm saturated output power when operated from a 3.2 V dc supply voltage at 78 GHz.

A 75-81 GHz, 14.3 dBm Peak Output Power, 21 dB Peak Gain, SiGe Power-Combining Amplifier Operating from a Single 3.3 V Supply

A compact differential 4-way power combiner with 2.3 dB loss and high common-mode rejection characteristic for use in mm-wave PAs is presented. A complete circuit comprised of a power splitter, two-stage cascode PA array, and a power combiner was implemented in SiGe technology. Measured small-signal gain of at least 17 dB was obtained from 74.5 GHz to 80.5 GHz with a peak 21 dB at 79 GHz. The prototype delivered 13.2 dBm P1dB and 14.3 dBm Psat when operated from a single 3.3 V supply at 75 GHz.

A SiGe Power Amplifier with Integrated BALUNs for 81-86 GHz E-Band Backhaul Applications

The design of a two-stage differential cascode power amplifier (PA) for 81-86 GHz E-band applications is presented. The PA was realised in SiGe technology with fT/fmax 170/250 GHz. A broadband transformer with efficiency higher than 79.4% from 71 GHz to 96 GHz is used as a BALUN. The PA delivers a 4.5 dBm saturated output power and exhibits a 13.4 dB gain at 83.6 GHz. The input and output return losses agree well with the design specifications.

Holistic design of 8-way combining transformers in SiGe technology for use in millimetre-wave power amplifiers

This paper presents the design of a novel 8-way power-combining transformer for use in mm-wave power amplifier (PA). The combiner exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. A complete circuit comprised of a power splitter, two-stage cascode PA array, a power combiner and input/output matching elements was designed and realized in SiGe technology. Measured gain of at least 16.8 dB was obtained from 76.4 GHz to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm OP and 14 dBm saturated output power when operated from a 3.2 V DC supply voltage at 78 GHz. © 2013 IEEE.

Projecto de receptores integrados de banda larga

O presente trabalho tem como objectivo o estudo e projecto de receptores optimizados para sistemas de comunicações por fibra óptica de muito alto débito (10Gb/s e 40Gb/s), com a capacidade integrada de compensação adaptativa pós-detecção da distorção originada pela característica de dispersão cromática e de polarização do canal óptico. O capítulo 1 detalha o âmbito de aplicabilidade destes receptores em sistemas de comunicações ópticas com multiplexagem no comprimento de onda (WDM) actuais. O capítulo apresenta ainda os objectivos e principais contribuições desta tese. O capítulo 2 detalha o projecto de um amplificador pós-detecção adequado para sistemas de comunicação ópticos com taxa de transmissão de 10Gb/s. São discutidas as topologias mais adequadas para amplificadores pós detecção e apresentados os critérios que ditaram a escolha da topologia de transimpedância bem como as condições que permitem optimizar o seu desempenho em termos de largura de banda, ganho e ruído. Para além disso são abordados aspectos relacionados com a implementação física em tecnologia monolítica de microondas (MMIC), focando em particular o impacto destes no desempenho do circuito, como é o caso do efeito dos componentes extrínsecos ao circuito monolítico, em particular as ligações por fio condutor do monólito ao circuito externo. Este amplificador foi projectado e produzido em tecnologia pHEMT de Arsenieto de Gálio e implementado em tecnologia MMIC. O protótipo produzido foi caracterizado na fábrica, ainda na bolacha em que foi produzido (on-wafer) tendo sido obtidos dados de caracterização de 80 circuitos protótipo. Estes foram comparados com resultados de simulação e com desempenho do protótipo montado num veículo de teste. O capítulo 3 apresenta o projecto de dois compensadores eléctricos ajustáveis com a capacidade de mitigar os efeitos da dispersão cromática e da dispersão de polarização em sistemas ópticos com débito binário de 10Gb/s e 40Gb/s, com modulação em banda lateral dupla e banda lateral única. Duas topologias possíveis para este tipo de compensadores (a topologia Feed-Forward Equalizer e a topologia Decision Feedback Equaliser) são apresentadas e comparadas. A topologia Feed-Forward Equaliser que serviu de base para a implementação dos compensadores apresentados é analisada com mais detalhe sendo propostas alterações que permitem a sua implementação prática. O capítulo apresenta em detalhe a forma como estes compensadores foram implementados como circuitos distribuídos em tecnologia MMIC sendo propostas duas formas de implementar as células de ganho variável: com recurso à configuração cascode ou com recurso à configuração célula de Gilbert. São ainda apresentados resultados de simulação e experimentais (dos protótipos produzidos) que permitem tirar algumas conclusões sobre o desempenho das células de ganho com as duas configurações distintas. Por fim, o capítulo inclui ainda resultados de desempenho dos compensadores testados como compensadores de um sinal eléctrico afectado de distorção. No capítulo 4 é feita uma análise do impacto da modulação em banda lateral dupla (BLD) em comparação com a modulação em banda lateral única (BLU) num sistema óptico afectado de dispersão cromática e de polarização. Mostra-se que com modulação em BLU, como não há batimento entre portadoras das duas bandas laterais em consequência do processo quadrático de detecção e há preservação da informação da distorção cromática do canal (na fase do sinal), o uso deste tipo de modulação em sistemas de comunicação óptica permite maior tolerância à dispersão cromática e os compensadores eléctricos são muito mais eficientes. O capítulo apresenta ainda resultados de teste dos compensadores desenvolvidos em cenários experimentais de laboratório representativos de sistemas ópticos a 10Gb/s e 40Gb/s. Os resultados permitem comparar o desempenho destes cenários sem e com compensação eléctrica optimizada, para os casos de modulação em BLU e em BLD, e considerando ainda os efeitos da dispersão na velocidade de grupo e do atraso de grupo diferencial. Mostra-se que a modulação BLU em conjunto com compensação adaptativa eléctrica permite um desempenho muito superior á modulação em BLD largamente utilizada nos sistemas de comunicações actuais. Por fim o capítulo 5 sintetiza e apresenta as principais conclusões deste trabalho.

Design and optimization of LNA topologies with image rejection filters

An important problem in designing RFIC in CMOS technology is the parasitic elements of passive and active devices that complicate design calculations. This article presents three LNA topologies including cascode, folded cascade, and differential cascode and then introduces image rejection filters for low-side and high-side injection. Then, a new method for design and optimization of the circuits based on a Pareto-based multiobjective genetic algorithm is proposed. A set of optimum device values and dimensions that best match design specifications are obtained. The optimization method is layout aware, parasitic aware, and simulation based. Circuit simulations are carried out based on TSMC 0.18 um CMOS technology by using Hspice.