A simple analog controller for single-phase half-bridge rectifier and its application to transformerless UPS

A simple, low-cost, constant frequency, analog controller is proposed for the front-end half-bridge rectifier of a single-phase transformerless UPS system to maintain near unity power factor at the input and zero dc-offset voltage at the output. The controller generates the required gating pulses by comparing the input current with a periodic, bipolar, linear carrier without sensing the input voltage. Two voltage controllers and a single integrator with reset are used to generate the required carrier. All the necessary control operations can be performed without using any PLL, multiplier and/or divider. The controller can be fabricated as a single integrated circuit. The control concept is validated through simulation and also experimentally on an 800W half-bridge rectifier. Experimental results are presented for ac-dc application, and also for ac-dc-ac UPS application with both sinusoidal and nonlinear loads. The simulation and experimental results agree well.

Conformation of a 16-residue zervamicin IIA analog peptide containing three different structural features: 310-helix, alpha helix and ß-bend ribbon

Boc-Trp-Ile-Ala-Aib-Ile-Val-Aib-Leu-Aib- Pro-Ala-Aib-Pro-Aib-Pro-Phe-OM(we here Boc is t-butoxycarbonyla nd Aib is a-aminoisobutyriac cid), a synthetica polar analog of the membrane-activefu ngal peptide antibioticz ervamtycinII A, crystallizesi n spaceg roupP 1 withZ =1 and cell parameters a = 9.086 ?0.002 A, b = 10.410 ?+ 0.002 A, c = 28.188 ? 0.004 A, a = 86.13 ? 0.01?, 13 = 87.90 ? 0.01?, and y = 89.27 ? 0.01?;o veralla greementf actorR = 7.3% for 7180 data (Fo > 3cr) and 0.91-A resolution. The peptide backbone makes a continuous spiral that begins as a 310-helix at the N-terminus, changes to an a-helix for two turns, and ends in a spiral of three fl-bends in a ribbon. Each of the fl-bends contains a proline residue at one of the corners. The torsion angles 4i range from -51? to -91? (average value -64o), and the torsion angles ai range from -1? to -46? (average value -31?). There are 10 intramolecularN H...OCh ydrogenb onds in the helix and two directh ead-to-taihl ydrogenb ondsb etween successive molecules. Two H20 and two CH30H solvent molecules fill additional space with appropriate hydrogen bonding in the head-to-tail region, and two additional H20 molecules form hydrogen bonds with carbonyl oxygens near the curve in the helix at Pro-10. Since there is only one peptide molecule per cell in space group P1, the molecules repeat only by translation, and consequently the helices pack parallel to each other.

A Sub-Nyquist Sampling Method For Computing The Level-crossing-times Of An Analog Signal: Theory And Applications

We address the problem of computing the level-crossings of an analog signal from samples measured on a uniform grid. Such a problem is important, for example, in multilevel analog-to-digital (A/D) converters. The first operation in such sampling modalities is a comparator, which gives rise to a bilevel waveform. Since bilevel signals are not bandlimited, measuring the level-crossing times exactly becomes impractical within the conventional framework of Shannon sampling. In this paper, we propose a novel sub-Nyquist sampling technique for making measurements on a uniform grid and thereby for exactly computing the level-crossing times from those samples. The computational complexity of the technique is low and comprises simple arithmetic operations. We also present a finite-rate-of-innovation sampling perspective of the proposed approach and also show how exponential splines fit in naturally into the proposed sampling framework. We also discuss some concrete practical applications of the sampling technique.

Optimal Power and Noise for Analog and Digital Sections of a Low Power Radio Receiver

We determine the optimal allocation of power between the analog and digital sections of an RF receiver while meeting the BER constraint. Unlike conventional RF receiver designs, we treat the SNR at the output of the analog front end (SNRAD) as a design parameter rather than a specification to arrive at this optimal allocation. We first determine the relationship of the SNRAD to the resolution and operating frequency of the digital section. We then use power models for the analog and digital sections to solve the power minimization problem. As an example, we consider a 802.15.4 compliant low-IF receiver operating at 2.4 GHz in 0.13 μm technology with 1.2 V power supply. We find that the overall receiver power is minimized by having the analog front end provide an SNR of 1.3dB and the ADC and the digital section operate at 1-bit resolution with 18MHz sampling frequency while achieving a power dissipation of 7mW.

An analog MVUE for a wireless sensor network

An analog minimum-variance unbiased estimator(MVUE) over an asymmetric wireless sensor network is studied.Minimisation of variance is cast into a constrained non-convex optimisation problem. An explicit algorithm that solves the problem is provided. The solution is obtained by decomposing the original problem into a finite number of convex optimisation problems with explicit solutions. These solutions are then juxtaposed together by exploiting further structure in the objective function.

Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits

Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

V-Transform: “An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits

Abstract—DC testing of parametric faults in non-linear analog circuits based on a new transformation, entitled, V-Transform acting on polynomial coefficient expansion of the circuit function is presented. V-Transform serves the dual purpose of monotonizing polynomial coefficients of circuit function expansion and increasing the sensitivity of these coefficients to circuit parameters. The sensitivity of V-Transform Coefficients (VTC) to circuit parameters is up to 3x-5x more than sensitivity of polynomial coefficients. As a case study, we consider a benchmark elliptic filter to validate our method. The technique is shown to uncover hitherto untestable parametric faults whose sizes are smaller than 10 % of the nominal values. I.

Analog/RF Built-in-Self-Test Subsystem for a Mobile Broadcast Video Receiver in 65-nm CMOS

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which makes pass/fail determination on parts, resulting in significant test time and cost reduction.

Extrinsic Analog Synthesis using Piecewise Linear Current-Mode Circuits

A methodology is presented for the synthesis of analog circuits using piecewise linear (PWL) approximations. The function to be synthesized is divided into PWL segments such that each segment can be realized using elementary MOS current-mode programmable-gain circuits. A number of these elementary current-mode circuits when connected in parallel, it is possible to realize piecewise linear approximation of any arbitrary analog function with in the allowed approximation error bounds. Simulation results show a close agreement between the desired function and the synthesized output. The number of PWL segments used for approximation and hence the circuit area is determined by the required accuracy and the smoothness of the resulting function.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.