171 resultados para WLAN
Resumo:
In a typical enterprise WLAN, a station has a choice of multiple access points to associate with. The default association policy is based on metrics such as Re-ceived Signal Strength(RSS), and “link quality” to choose a particular access point among many. Such an approach can lead to unequal load sharing and diminished system performance. We consider the RAT (Rate And Throughput) policy [1] which leads to better system performance. The RAT policy has been implemented on home-grown centralized WLAN controller, ADWISER [2] and we demonstrate that the RAT policy indeed provides a better system performance.
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This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.
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Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z
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This paper presents a 5GHz double-balanced mixer with DC-offset cancellation circuit for direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard. The analog feedback loop is used, to eliminate the DC-offset at the output of the double-balanced mixer. The test results show that the mixer with DC-offset cancellation circuit has voltage conversion gain of 9.5dB at 5.15GHz, noise figure of 13.5dB, IIP3 of 7.6 dBm, 1.73mV DC-offset voltage and 67mW power with 3.3-V power supply. The DC-offset cancellation circuit has less than 0.1mm(2) additional area and 0.3mW added power dissipation. The direct conversion WLAN receiver has been implemented in a 0.35 mu m SiGe BiCMOS technology.
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In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.
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A low-cost low-power single chip WLAN 802.11a transceiver is designed for personal communication terminal and local multimedia data transmission. It has less than 130mA current dissipation, maximal 67dB gain and can be programmed to be 20dB minimal gain. The receiver system noise figure is 6.4dB in hige-gain mode.
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A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.
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A 5.2 GHz variable-gain amplifier (VGA) and a power amplifier (PA) driver are designed for WLAN IEEE 802.11a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 μm SiGe BiCMOS technology and occupy 1.12×1.25 mm~2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point (OIP3) of 11 dBm. The gain drift over the temperature varying from -30 to 85℃ converges within±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.
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A novel wireless local area network (WLAN) security processor is described in this paper. It is designed to offload security encapsulation processing from the host microprocessor in an IEEE 802.11i compliant medium access control layer to a programmable hardware accelerator. The unique design, which comprises dedicated cryptographic instructions and hardware coprocessors, is capable of performing wired equivalent privacy, temporal key integrity protocol, counter mode with cipher block chaining message authentication code protocol, and wireless robust authentication protocol. Existing solutions to wireless security have been implemented on hardware devices and target specific WLAN protocols whereas the programmable security processor proposed in this paper provides support for all WLAN protocols and thus, can offer backwards compatibility as well as future upgrade ability as standards evolve. It provides this additional functionality while still achieving equivalent throughput rates to existing architectures. © 2006 IEEE.
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Wireless enabled portable devices must operate with the highest possible energy efficiency while still maintaining a minimum level and quality of service to meet the user's expectations. The authors analyse the performance of a new pointer-based medium access control protocol that was designed to significantly improve the energy efficiency of user terminals in wireless local area networks. The new protocol, pointer controlled slot allocation and resynchronisation protocol (PCSAR), is based on the existing IEEE 802.11 point coordination function (PCF) standard. PCSAR reduces energy consumption by removing the need for power saving stations to remain awake and listen to the channel. Using OPNET, simulations were performed under symmetric channel loading conditions to compare the performance of PCSAR with the infrastructure power saving mode of IEEE 802.11, PCF-PS. The simulation results demonstrate a significant improvement in energy efficiency without significant reduction in performance when using PCSAR. For a wireless network consisting of an access point and 8 stations in power saving mode, the energy saving was up to 31% while using PCSAR instead of PCF-PS, depending upon frame error rate and load. The results also show that PCSAR offers significantly reduced uplink access delay over PCF-PS while modestly improving uplink throughput.
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Indoor wireless network based client localisation requires the use of a radio map to relate received signal strength to specific locations. However, signal strength measurements are time consuming, expensive and usually require unrestricted access to all parts of the building concerned. An obvious option for circumventing this difficulty is to estimate the radio map using a propagation model. This paper compares the effect of measured and simulated radio maps on the accuracy of two different methods of wireless network based localisation. The results presented indicate that, although the propagation model used underestimated the signal strength by up to 15 dB at certain locations, there was not a signigicant reduction in localisation performance. In general, the difference in performance between the simulated and measured radio maps was around a 30 % increase in rms error