Disseny i construcció d’ un braç de robot de 5 graus de llibertat governat des de PC via USB.

El braç robot es va crear com a resposta a una necessitat de fabricació d’elements mitjançant la producció en cadena i en tasques que necessiten precisió. Hi ha, però, altres tipus de tasques les quals no són repetitives, ni poden ésser programades, que necessiten però ser controlades en tot moment per un ésser humà. Són activitats que han d’estar realitzades per un ésser humà, però que requereixen molta precisió, és per això que es creu necessari el disseny d’un prototipus de control d’un braç robot estàndard, que permeti a una persona el control total sobre aquest en temps real per a la realització d’una tasca no repetitiva i no programable prèviament. Pretenem, en el present projecte, dissenyar i construir un braç robot de 5 graus de llibertat, controlat des d’un PC mitjançant un microcontrolador PIC amb comunicació a través d’un bus USB. El robot serà governat des d’un PC a través d’un software de control específic

Baja SAE USB como caso de aprendizaje orientado por proyectos desde el paradigma de la complejidad

Resumen basado en el de la publicaci??n

Fixed point dual carrier modulation performance for wireless USB

Dual Carrier Modulation (DCM) is currently used as the higher data rate modulation scheme for Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) in the ECMA-368 defined Ultra-Wideband (UWB) radio platform. ECMA-368 has been chosen as the physical radio platform for many systems including Wireless USB (W-USB), Bluetooth 3.0 and Wireless HDMI; hence ECMA-368 is an important issue to consumer electronics and the user’s experience of these products. In this paper, Log Likelihood Ratio (LLR) demapping method is used for the DCM demaper implemented in fixed point model. Channel State Information (CSI) aided scheme coupled with the band hopping information is used as the further technique to improve the DCM demapping performance. The receiver performance for the fixed point DCM is simulated in realistic multi-path environments.

A Packet/Frame sync detector based on statistical mode with application to wireless-USB

Wireless Personal Area Networks (WPANs) are offering high data rates suitable for interconnecting high bandwidth personal consumer devices (Wireless HD streaming, Wireless-USB and Bluetooth EDR). ECMA-368 is the Physical (PHY) and Media Access Control (MAC) backbone of many of these wireless devices. WPAN devices tend to operate in an ad-hoc based network and therefore it is important to successfully latch onto the network and become part of one of the available piconets. This paper presents a new algorithm for detecting the Packet/Fame Sync (PFS) signal in ECMA-368 to identify piconets and aid symbol timing. The algorithm is based on correlating the received PFS symbols with the expected locally stored symbols over the 24 or 12 PFS symbols, but selecting the likely TFC based on the highest statistical mode from the 24 or 12 best correlation results. The results are very favorable showing an improvement margin in the order of 11.5dB in reference sensitivity tests between the required performance using this algorithm and the performance of comparable systems.

Dual carrier modulation demapping methods and performances for wireless USB

Dual Carrier Modulation (DCM) was chosen as the higher data rate modulation scheme for MB-OFDM (Multiband Orthogonal Frequency Division Multiplexing) in the UWB (Ultra-Wide Band) radio platform ECMA-368. ECMA-368 has been chosen as the physical implementation for high data rate Wireless USB (W-USB) and Bluetooth 3.0. In this paper, different demapping methods for the DCM demapper are presented, being Soft Bit, Maximum Likely (ML) Soft Bit and Log Likelihood Ratio (LLR). Frequency diversity and Channel State Information (CSI) are further techniques to enhance demapping methods. The system performance for those DCM demapping methods simulated in realistic multi-path environments are provided and compared.

Enhanced three-factor security protocol for consumer USB mass storage devices

The Universal Serial Bus (USB) is an extremely popular interface standard for computer peripheral connections and is widely used in consumer Mass Storage Devices (MSDs). While current consumer USB MSDs provide relatively high transmission speed and are convenient to carry, the use of USB MSDs has been prohibited in many commercial and everyday environments primarily due to security concerns. Security protocols have been previously proposed and a recent approach for the USB MSDs is to utilize multi-factor authentication. This paper proposes significant enhancements to the three-factor control protocol that now makes it secure under many types of attacks including the password guessing attack, the denial-of-service attack, and the replay attack. The proposed solution is presented with a rigorous security analysis and practical computational cost analysis to demonstrate the usefulness of this new security protocol for consumer USB MSDs.

Efficient biometric and password based mutual authentication for consumer USB mass storage devices

A Universal Serial Bus (USB) Mass Storage Device (MSD), often termed a USB flash drive, is ubiquitously used to store important information in unencrypted binary format. This low cost consumer device is incredibly popular due to its size, large storage capacity and relatively high transfer speed. However, if the device is lost or stolen an unauthorized person can easily retrieve all the information. Therefore, it is advantageous in many applications to provide security protection so that only authorized users can access the stored information. In order to provide security protection for a USB MSD, this paper proposes a session key agreement protocol after secure user authentication. The main aim of this protocol is to establish session key negotiation through which all the information retrieved, stored and transferred to the USB MSD is encrypted. This paper not only contributes an efficient protocol, but also does not suffer from the forgery attack and the password guessing attack as compared to other protocols in the literature. This paper analyses the security of the proposed protocol through a formal analysis which proves that the information is stored confidentially and is protected offering strong resilience to relevant security attacks. The computational cost and communication cost of the proposed scheme is analyzed and compared to related work to show that the proposed scheme has an improved tradeoff for computational cost, communication cost and security.

Mobile phone-based electrochemiluminescence sensing exploiting the 'USB On-The-Go' protocol

A low-cost system to generate, control and detect electrochemiluminescence using a mobile smartphone is described. A simple tone-detection integrated circuit is used to switch power sourced from the phone's Universal Serial Bus (USB) 'On-The-Go' (OTG) port, using audible tone pulses played over the device's audio jack. We have successfully applied this approach to smartphones from different manufacturers and with different operating system versions. ECL calibrations of a common luminophore, tris(2,2′-bipyridine)ruthenium(II) ([Ru(bpy)3]²⁺), with 2-(dibutylamino)ethanol (DBAE) as a co-reactant, showed no significant difference in light intensities when an electrochemical cell was controlled by a mobile phone in this manner, compared to the same calibration generated using a conventional potentiostat. Combining this novel approach to control the applied potential with the measurement of the emitted light through the smart phone camera (using an in-house built Android app), we explored the ECL properties of a water-soluble iridium(III) complex that emits in the blue region of the spectrum. The iridium(III) complex exhibited superior co-reactant ECL intensities and limits of detection to that of the conventional [Ru(bpy)3]²⁺ luminophore.

Ottimizzazione di protocolli di trasmissione dati tramite interfaccia usb implementati su fpga

La maggior parte dei moderni dispositivi e macchinari, sia ad uso civile che industriale, utilizzano sistemi elettronici che ne supervisionano e ne controllano il funzionamento. All’ interno di questi apparati è quasi certamente impiegato un sistema di controllo digitale che svolge, anche grazie alle potenzialità oggi raggiunte, compiti che fino a non troppi anni or sono erano dominio dell’ elettronica analogica, si pensi ad esempio ai DSP (Digital Signal Processor) oggi impiegati nei sistemi di telecomunicazione. Nonostante l'elevata potenza di calcolo raggiunta dagli odierni microprocessori/microcontrollori/DSP dedicati alle applicazioni embedded, quando è necessario eseguire elaborazioni complesse, time-critical, dovendo razionalizzare e ottimizzare le risorse a disposizione, come ad esempio spazio consumo e costi, la scelta ricade inevitabilmente sui dispositivi FPGA. I dispositivi FPGA, acronimo di Field Programmable Gate Array, sono circuiti integrati a larga scala d’integrazione (VLSI, Very Large Scale of Integration) che possono essere configurati via software dopo la produzione. Si differenziano dai microprocessori poiché essi non eseguono un software, scritto ad esempio in linguaggio assembly oppure in linguaggio C. Sono invece dotati di risorse hardware generiche e configurabili (denominate Configurable Logic Block oppure Logic Array Block, a seconda del produttore del dispositivo) che per mezzo di un opportuno linguaggio, detto di descrizione hardware (HDL, Hardware Description Language) vengono interconnesse in modo da costituire circuiti logici digitali. In questo modo, è possibile far assumere a questi dispositivi funzionalità logiche qualsiasi, non previste in origine dal progettista del circuito integrato ma realizzabili grazie alle strutture programmabili in esso presenti.

Generatore di entropia basato su dinamica caotica con interfaccia usb

È impossibile implementare sorgenti autenticamente casuali su hardware digitale. Quindi, storicamente, si è fatto ampio uso di generatori di numeri pseudo-casuali, evitando così i costi necessari per la progettazione di hardware analogico dedicato. Tuttavia, le sorgenti pseudo-casuali hanno proprietà (riproducibilità e periodicità) che si trasformano in vulnerabilità, nel caso in cui vengano adottate in sistemi di sicurezza informatica e all’interno di algoritmi crittografici. Oggi la richiesta di generatori di numeri autenticamente casuali è ai suoi massimi storici. Alcuni importanti attori dell’ICT sviluppato proprie soluzioni dedicate, ma queste sono disponibili solo sui sistemi moderni e di fascia elevata. È quindi di grande attualità rendere fruibili generatori autenticamente casuali per sistemi già esistenti o a basso costo. Per garantire sicurezza e al tempo stesso contenere i costi di progetto è opportuno pensare ad architetture che consentano di riusare parti analogiche già disponibili. Particolarmente interessanti risultano alcune architetture che, grazie all’utilizzo di dinamiche caotiche, consentono di basare buona parte della catena analogica di elaborazione su ADC. Infatti, tali blocchi sono ampiamente fruibili in forma integrata su architetture programmabili e microcontrollori. In questo lavoro, si propone un’implementazione a basso costo ed elevata flessibilità di un architettura basata su un ADC, inizialmente concepita all’Università di Bologna. La riduzione di costo viene ottenuta sfruttando il convertitore già presente all’interno di un microcontrollore. L’elevata flessibilità deriva dal fatto che il microcontrollore prescelto mette a disposizione una varietà di interfacce di comunicazione, tra cui quella USB, con la quale è possibile rendere facilmente fruibili i numeri casuali generati. Quindi, l’intero apparato comprende solo un microcontrollore e una minima catena analogica di elaborazione esterna e può essere interfacciato con estrema facilità ad elaboratori elettronici o sistemi embedded. La qualità della proposta, in termini di statistica delle sequenze casuali generate, è stata validata sfruttando i test standardizzati dall’U.S. NIST.

USB monitor in LabVIEW per il controllo remoto delle schede DAQ del pixel detector di ATLAS

L’esperimento ATLAS al CERN di Ginevra ha un complesso sistema di rivelatori che permettono l’acquisizione e il salvataggio di dati generati dalle collisioni di particelle fondamentali. Il rivelatore per cui trova una naturale applicazione il lavoro di questa tesi è il Pixel Detector. Esso è il più vicino alla beam pipe e si compone di più strati, il più interno dei quali, l’Insertable B-Layer (IBL), aggiunto in seguito allo shut down dell’LHC avvenuto nel 2013, ha apportato diverse innovazioni per migliorare la risoluzione spaziale delle tracce e la velocità di acquisizione dei dati. E’ stato infatti necessario modificare il sistema di acquisizione dati dell’esperimento aggiungendo nuove schede chiamate ROD, ReadOut Driver, e BOC, Back Of Crate. Entrambe le due tipologie di schede sono montate su un apparato di supporto, chiamato Crate, che le gestisce. E’ evidente che avere un sistema remoto che possa mostrare in ogni momento il regime di funzionamento del crate e che dia la possibilità di pilotarlo anche a distanza risulta estremamente utile. Così, tramite il linguaggio di programmazione LabVIEW è stato possibile progettare un sistema multipiattaforma che permette di comunicare con il crate in modo da impostare e ricevere svariati parametri di controllo del sistema di acquisizione dati, come ad esempio la temperatura, la velocità delle ventole di raffreddamento e le correnti assorbite dalle varie tensioni di alimentazione. Al momento il software viene utilizzato all’interno dell’Istituto Nazionale di Fisica Nucleare (INFN) di Bologna dove è montato un crate W-Ie-Ne-R, speculare a quello presente al CERN di Ginevra, contenente delle schede ROD e BOC in fase di test. Il progetto ed il programma sviluppato e presentato in questa tesi ha ulteriori possibilità di miglioramento e di utilizzo, dal momento che anche per altri esperimenti dell’LHC le schede di acquisizione vengono montate sullo stesso modello di crate.

Logical simulation of communication subsystem for Universal Serial Bus (USB)

The primary purpose of this thesis was to design a logical simulation of a communication sub block to be used in the effective communication of digital data between the host and the peripheral devices. The module designed is a Serial interface engine in the Universal Serial Bus that effectively controls the flow of data for communication between the host and the peripheral devices with the emphasis on the study of timing and control signals, considering the practical aspects of them. In this study an attempt was made to realize data communication in the hardware using the Verilog Hardware Description language, which is supported by most popular logic synthesis tools. Various techniques like Cyclic Redundancy Checks, bit-stuffing and Non Return to Zero are implemented in the design to provide enhanced performance of the module.

AITPM Email Newsletter Volume 0905, May 2009: Presidents Message

President’s Message Hello fellow AITPM members, We’ve been offered a lot of press lately about the Federal Government’s plan for the multibillion dollar rollout of its high speed broadband network, which at the moment is being rated to a speed of 100Mb/s. This seems fantastic in comparison to the not atypical 250 to 500kb/s that I receive on my metropolitan cable broadband, which incidentally my service provider rates at theoretical speeds of up to 8 Mb/s. I have no doubt that such a scheme will generate significant advantages to business and consumers. However, I also have some reservations. Only a few of years ago I marvelled at my first 256Mb USB stick, which cost my employer about $90. Last month I purchased a 16Gb stick with a free computer carry bag for $80, which on the back of my envelope has given me about 72 times the value of my first USB stick not including the carry bag! I am pretty sure the technology industry will find a way to eventually push a lot more than 100Mb/s down the optic fibre network just as they have done with pushing several Mb/s ADSL2 down antique copper wire. This makes me wonder about the general problem of inbuilt obsolescence of all things high-tech due to rapid advances in the tech industry. As a transport professional I then think to myself that our industry has been moving forward at somewhat of a slower pace. We certainly have had major milestones having significant impacts, such as the move from horse and cart to the self propelled motor vehicle, sealing and formal geometric design of roads, development of motorways, signalisation of intersections, coordination of networks, to simulation modelling for real time adaptive control (perhaps major change has been at a frequency of 30 years or so?). But now with ITS truly penetrating the transport market, largely thanks to the in-car GPS navigator, smart phone, e-toll and e-ticket, I believe that to avoid our own obsolescence we’re going to need to “plan for ITS” rather than just what we seem to have been doing up until now, that is, to get it out there. And we’ll likely need to do it at a faster pace. It will involve understanding how to data mine enormous data sets, better understanding the human/machine interface, keeping pace with automotive technology more closely, resolving the ethical and privacy chestnuts, and in the main actually planning for ITS to make peoples’ lives easier rather than harder. And in amongst this we’ll need to keep pace with the types of technology advances similar to my USB stick example above. All the while we’ll be making a brand new set of friends in the disciplines that will morph into ITS along with us. Hopefully these will all be “good” problems for our profession to have. I should close in reminding everyone again that AITPM’s flagship event, the 2009 AITPM National Conference, Traffic Beyond Tomorrow, is being held in Adelaide from 5 to 7 August. www.aitpm.com has all of the details about how to register, sponsor a booth, session, etc. Best regards all, Jon Bunker