Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Interfaces and traps in pentacene field-effect transistor

The equivalent circuit parameters for a pentacene organic field-effect transistor are determined from low frequency impedance measurements in the dark as well as under light illumination. The source-drain channel impedance parameters are obtained from Bode plot analysis and the deviations at low frequency are mainly due to the contact impedance. The charge accumulation at organic semiconductor-metal interface and dielectric-semiconductor interface is monitored from the response to light as an additional parameter to find out the contributions arising from photovoltaic and photoconductive effects. The shift in threshold voltage is due to the accumulation of photogenerated carriers under source-drain electrodes and at dielectric-semiconductor interface, and also this dominates the carrier transport. The charge carrier trapping at various interfaces and in the semiconductor is estimated from the dc and ac impedance measurements under illumination. (c) 2010 American Institute of Physics. doi: 10.1063/1.3517085]

Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire Transistor

In this paper, a physically based analytical quantum linear threshold voltage model for short channel quad gate MOSFETs is developed. The proposed model, which is suitable for circuit simulation, is based on the analytical solution of 3-D Poisson and 2-D Schrodinger equation. Proposed model is fully validated against the professional numerical device simulator for a wide range of device geometries and also used to analyze the effect of geometry variation on the threshold voltage.

Performance Enhancement of the Tunnel Field Effect Transistor using SiGe Source

Due to extremely low off state current (IOFF) and excellent sub-threshold characteristics, the tunnel field effect transistor (TFET) has attracted a lot of attention for low standby power applications. In this work, we aim to increase the on state current (ION) of the device. A novel device architecture with a SiGe source is proposed. The proposed structure shows an order of improvement in ION compared to the conventional Si structure. A process flow adaptable to conventional CMOS technology is also addressed.

Low threshold voltage ZnO thin film transistor with a Zn0.7Mg0.3O gate dielectric for transparent electronics

A highly transparent all ZnO thin film transistor (ZnO-TFT) with a transmittance of above 80% in the visible part of the spectrum, was fabricated by direct current magnetron sputtering, with a bottom gate configuration. The ZnO-TFT with undoped ZnO channel layers deposited on 300 nm Zn0.7Mg0.3O gate dielectric layers attains an on/off ratio of 104 and mobility of 20 cm2/V s. The capacitance-voltage (C−V) characteristics of the ZnO-TFT exhibited a transition from depletion to accumulation with a small hysteresis indicating the presence of oxide traps. The trap density was also computed from the Levinson’s plot. The use of Zn0.7Mg0.3O as a dielectric layer adds additional dimension to its applications. The room temperature processing of the device depicts the possibility of the use of flexible substrates such as polymer substrates. The results provide the realization of transparent electronics for next-generation optoelectronics.

Acenaphtho[1,2-b]quinoxaline based low band gap copolymers for organic thin film transistor applications

We report the synthesis of a novel class of low band gap copolymers based on anacenaphtho[1,2-b]quinoxaline core and oligothiophene derivatives acting as the acceptor and the donor moieties, respectively. The optical properties of the copolymers were characterized by ultraviolet-visible spectroscopy while the electrochemical properties were determined by cyclic voltammetry. The band gap of these polymers was found to be in the range 1.8-2.0 eV as calculated from the optical absorption band edge. X-ray diffraction measurements show weak pi-pi stacking interactions between the polymer chains. The hole mobility of the copolymers was evaluated using field-effect transistor measurements yielding values in the range 10(-5)-10(-3) cm(2)/Vs.

Symmetry-dependent phonon renormalization in monolayer MoS2 transistor

A strong electron-phonon interaction which limits the electronic mobility of semiconductors can also have significant effects on phonon frequencies. The latter is the key to the use of Raman spectroscopy for nondestructive characterization of doping in graphene-based devices. Using in situ Raman scattering from a single-layer MoS2 electrochemically top-gated field-effect transistor (FET), we show softening and broadening of the A(1g) phonon with electron doping, whereas the other Raman-active E-2g(1) mode remains essentially inert. Confirming these results with first-principles density functional theory based calculations, we use group theoretical arguments to explain why the A(1g) mode specifically exhibits a strong sensitivity to electron doping. Our work opens up the use of Raman spectroscopy in probing the level of doping in single-layer MoS2-based FETs, which have a high on-off ratio and are of technological significance.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

Observation of trap-assisted space charge limited conductivity in short channel MoS2 transistor

We present temperature dependent I-V measurements of short channel MoS2 field effect devices at high source-drain bias. We find that, although the I-V characteristics are ohmic at low bias, the conduction becomes space charge limited at high V-DS, and existence of an exponential distribution of trap states was observed. The temperature independent critical drain-source voltage (V-c) was also determined. The density of trap states was quantitatively calculated from V-c. The possible origin of exponential trap distribution in these devices is also discussed. (C) 2013 AIP Publishing LLC.

Negative differential resistance and effect of defects and deformations in MoS2 armchair nanoribbon metal-oxide-semiconductor field effect transistor

In this work, we present a study on the negative differential resistance (NDR) behavior and the impact of various deformations (like ripple, twist, wrap) and defects like vacancies and edge roughness on the electronic properties of short-channel MoS2 armchair nanoribbon MOSFETs. The effect of deformation (3 degrees-7 degrees twist or wrap and 0.3-0.7 angstrom ripple amplitude) and defects on a 10 nm MoS2 ANR FET is evaluated by the density functional tight binding theory and the non-equilibrium Green's function approach. We study the channel density of states, transmission spectra, and the I-D-V-D characteristics of such devices under the varying conditions, with focus on the NDR behavior. Our results show significant change in the NDR peak to valley ratio and the NDR window with such minor intrinsic deformations, especially with the ripple. (C) 2013 AIP Publishing LLC.

Performance analysis of boron nitride embedded armchair graphene nanoribbon metal-oxide-semiconductor field effect transistor with Stone Wales defects

We study the performance of a hybrid Graphene-Boron Nitride armchair nanoribbon (a-GNR-BN) n-MOSFET at its ballistic transport limit. We consider three geometric configurations 3p, 3p + 1, and 3p + 2 of a-GNR-BN with BN atoms embedded on either side (2, 4, and 6 BN) on the GNR. Material properties like band gap, effective mass, and density of states of these H-passivated structures are evaluated using the Density Functional Theory. Using these material parameters, self-consistent Poisson-Schrodinger simulations are carried out under the Non Equilibrium Green's Function formalism to calculate the ballistic n-MOSFET device characteristics. For a hybrid nanoribbon of width similar to 5 nm, the simulated ON current is found to be in the range of 265 mu A-280 mu A with an ON/OFF ratio 7.1 x 10(6)-7.4 x 10(6) for a V-DD = 0.68 V corresponding to 10 nm technology node. We further study the impact of randomly distributed Stone Wales (SW) defects in these hybrid structures and only 2.5% degradation of ON current is observed for SW defect density of 3.18%. (C) 2014 AIP Publishing LLC.