999 resultados para Special architectures


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General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.

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The aim of this work is to propose a simple and efficient mechanism to deal with the problem of executing sequential code in a pure dataflow machine. Our results is obtained with a simulator of Wolf [4] architecture. The implemented mechanism improved the architecture performance when executing sequential code and we expect that this improvement could be better if we use some heuristics to deal with some special groups of instructions such as branch operations. Further research will show us if this is true.

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In this present work high quality PMMA opals with different sphere sizes, silica opals from large size spheres, multilayer opals, and inverse opals were fabricated. Highly monodisperse PMMA spheres were synthesized by surfactant-free emulsion polymerization (polydispersity ~2%). Large-area and well-ordered PMMA crystalline films with a homogenous thickness were produced by the vertical deposition method using a drawing device. Optical experiments have confirmed the high quality of these PMMA photonic crystals, e.g., well resolved high-energy bands of the transmission and reflectance spectra of the opaline films were observed. For fabrication of high quality opaline photonic crystals from large silica spheres (diameter of 890 nm), self-assembled in patterned Si-substrates a novel technique has been developed, in which the crystallization was performed by using a drawing apparatus in combination with stirring. The achievements comprise a spatial selectivity of opal crystallization without special treatment of the wafer surface, the opal lattice was found to match the pattern precisely in width as well as depth, particularly an absence of cracks within the size of the trenches, and finally a good three-dimensional order of the opal lattice even in trenches with a complex confined geometry. Multilayer opals from opaline films with different sphere sizes or different materials were produced by sequential crystallization procedure. Studies of the transmission in triple-layer hetero-opal revealed that its optical properties cannot only be considered as the linear superposition of two independent photonic bandgaps. The remarkable interface effect is the narrowing of the transmission minima. Large-area, high-quality, and robust photonic opal replicas from silicate-based inorganic-organic hybrid polymers (ORMOCER® s) were prepared by using the template-directed method, in which a high quality PMMA opal template was infiltrated with a neat inorganic-organic ORMOCER® oligomer, which can be photopolymerized within the opaline voids leading to a fully-developed replica structure with a filling factor of nearly 100%. This opal replica is structurally homogeneous, thermally and mechanically stable and the large scale (cm2 size) replica films can be handled easily as free films with a pair of tweezers.

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As a common reference for many in-development standards and execution frameworks, special attention is being paid to Service-Oriented Architectures. SOAs modeling, however, is an area in which a consensus has not being achieved. Currently, standardization organizations are defining proposals to offer a solution to this problem. Nevertheless, until very recently, non-functional aspects of services have not been considered for standardization processes. In particular, there exists a lack of a design solution that permits an independent development of the functional and non-functional concerns of SOAs, allowing that each concern be addressed in a convenient manner in early stages of the development, in a way that could guarantee the quality of this type of systems. This paper, leveraging on previous work, presents an approach to integrate security-related non-functional aspects (such as confidentiality, integrity, and access control) in the development of services.

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The goal of the RAP-WAM AND-parallel Prolog abstract architecture is to provide inference speeds significantly beyond those of sequential systems, while supporting Prolog semantics and preserving sequential performance and storage efficiency. This paper presents simulation results supporting these claims with special emphasis on memory performance on a two-level sharedmemory multiprocessor organization. Several solutions to the cache coherency problem are analyzed. It is shown that RAP-WAM offers good locality and storage efficiency and that it can effectively take advantage of broadcast caches. It is argued that speeds in excess of 2 ML IPS on real applications exhibiting medium parallelism can be attained with current technology.

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Possible switching architectures, with Optically Programmable Logic Cells - OPLCs - will be reported in this paper. These basic units, previously employed by us for some other applications mainly in optical computing, will be employed as main elements to switch optical communications signals. The main aspect to be considered is that because the nternal components of these cells have nonlinear behaviors, namely either pure bistable or SEED-like properties, several are the possibilities to be obtained. Moreover, because their properties are dependent, under certain condition, of the signal wavelength, they are apt to be employed in WDM systems and the final result will depend on the orresponding optical signal frequency. We will give special emphasis to the case where self-routing is achieved, namely to structures of the Batcher or Banyan type. In these cases, as it will be shown, there is the possibility to route any packet input to a certain direction according to its first bits. The number of possible outputs gives the number of bits needed to route signals. An advantage of this configuration is that a very versatile behavior may be allowed. The main one is the possibility to obtain configurations with different kinds of behavior, namely, Strictly Nonblocking, Wide-Sense Nonblocking or Rearrangeably Nonblocking as well as to eliminate switching conflicts at a certain intermediate stages.

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During the last three decades, FPGA technology has quickly evolved to become a major subject of research in computer and electrical engineering as it has been identified as a powerful alternative for creating highly efficient computing systems. FPGA devices offer substantial performance improvements when compared against traditional processing architectures via custom design and reconfiguration capabilities.

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Efficient hardware implementations of arithmetic operations in the Galois field are highly desirable for several applications, such as coding theory, computer algebra and cryptography. Among these operations, multiplication is of special interest because it is considered the most important building block. Therefore, high-speed algorithms and hardware architectures for computing multiplication are highly required. In this paper, bit-parallel polynomial basis multipliers over the binary field GF(2(m)) generated using type II irreducible pentanomials are considered. The multiplier here presented has the lowest time complexity known to date for similar multipliers based on this type of irreducible pentanomials.

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Item 247.

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It is a great pleasure to be Guest Editor for this issue – I hope that the papers which are included will be stimulating and support you in your ongoing research activities. A number of guiding principles were adopted in selecting the papers for inclusion in this issue. Firstly, the papers cover a wide range of logistics and supply chain management (SCM) topics. This is a reflection of the evolution of the field in recent years. In terms of the “buy-make-store-move-sell” model of SCM all the main constituent areas are addressed. Secondly, it is important that the conference issue of this Journal reflects the emphasis and content of the conference itself. I have tried to achieve this in terms of the papers included. One interesting point to note is that outsourcing is a theme which is a major issue in a number of papers. This reflects the increasing importance of this issue to organisations of all kinds and sizes. Economic globalisation and the trend towards vertical disintegration of supply chain architectures have sharpened the focus on outsourcing as a key element of supply chain strategy. The need to move beyond the notion that sourcing of certain activities can be some kind of panacea in evident from the relevant contributions. Thirdly, the LRN Annual Conference has become a more international event in recent years...the number of delegates and papers presented from outside the UK has continued to grow. The papers collected in this issue reflect this internationalization. Two papers are worthy of particular comment from an LRN perspective. The contribution by Jaafar and Rafiq has been developed from the submission which won the best paper prize at the LRN 2004 event. The paper by Pettit and Beresford is based on research which was supported by LRN seed corn funding. It was developed form the final report on this work submitted to CITL (UK) via the LRN. The seed corn funding is an important mechanism whereby the LRN supports research in innovative aspects of logistics in UK universities. In many ways, the LRN2004 event in Dublin seems like a long time ago. From my point of view it was one of the most professionally rewarding activities in which I have been involved in my career. It was a time to meet old friends and new and to keep abreast of the multitude of interesting projects being undertaken in over 20 countries. There are too many people to thank for the smooth running of the event. However, my colleague John Mee does warrant a special mention. His logistical skills were seriously put to the test in the weeks and months leading up to September 9th. 2004. I want to acknowledge his particular contribution to the success of the event. Since then we have had the 2005 event at the University of Plymouth. This was again a great opportunity to network with colleagues and many congratulations are due to John Dinwoodie and his team. We now look forward to LRN 2006 in Newcastle...form my part I hope and trust that this issue provides some useful perspectives and insights into the range of topics addressed.

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This research project set out to explore Unitary Authority (UA) involvement in festivals and special events across Wales. It considers the level and nature of UA involvement and investigates activity by event purpose; reasons for, and characteristics of, UA engagement; and, crucially, the extent and nature of event evaluation. The study’s aim was to begin the development of a baseline of information for further research into the growing use of festivals and special events as a strategy for local economic development in Wales. A quantitative survey approach facilitated a comprehensive snapshot of UA responses whilst also incorporating discursive elements. A telephone survey was designed and undertaken with representatives of all 22 UA departments responsible for festivals and events in Wales. The research reveals a significant level of festival and special event activity across Wales, supported primarily for its perceived socio-cultural value. However, evaluation would appear to be focused on improving processes and measuring economic outputs rather than assessing whether socio-cultural objectives are being achieved. Whilst overwhelmingly positive about efforts to improve approaches to evaluation, respondents held clear views about the complications most likely to hamper any such efforts. These responses focused upon the need for flexibility, cost effectiveness and comparability across festival and special event typologies.