Controle Adaptativo Robusto para Filtros Ativos de Potência Paralelo

Conventional control strategies used in shunt active power filters (SAPF) employs real-time instantaneous harmonic detection schemes which is usually implements with digital filters. This increase the number of current sensors on the filter structure which results in high costs. Furthermore, these detection schemes introduce time delays which can deteriorate the harmonic compensation performance. Differently from the conventional control schemes, this paper proposes a non-standard control strategy which indirectly regulates the phase currents of the power mains. The reference currents of system are generated by the dc-link voltage controller and is based on the active power balance of SAPF system. The reference currents are aligned to the phase angle of the power mains voltage vector which is obtained by using a dq phase locked loop (PLL) system. The current control strategy is implemented by an adaptive pole placement control strategy integrated to a variable structure control scheme (VS-APPC). In the VS-APPC, the internal model principle (IMP) of reference currents is used for achieving the zero steady state tracking error of the power system currents. This forces the phase current of the system mains to be sinusoidal with low harmonics content. Moreover, the current controllers are implemented on the stationary reference frame to avoid transformations to the mains voltage vector reference coordinates. This proposed current control strategy enhance the performance of SAPF with fast transient response and robustness to parametric uncertainties. Experimental results are showing for determining the effectiveness of SAPF proposed control system

Estratégia de controle robusto para filtro ativo paralelo sem detecção de harmônicos de correntes

Conventional control strategies used in shunt active power filters (SAPF) employs real-time instantaneous harmonic detection schemes which is usually implements with digital filters. This increase the number of current sensors on the filter structure which results in high costs. Furthermore, these detection schemes introduce time delays which can deteriorate the harmonic compensation performance. Differently from the conventional control schemes, this paper proposes a non-standard control strategy which indirectly regulates the phase currents of the power mains. The reference currents of system are generated by the dc-link voltage controller and is based on the active power balance of SAPF system. The reference currents are aligned to the phase angle of the power mains voltage vector which is obtained by using a dq phase locked loop (PLL) system. The current control strategy is implemented by an adaptive pole placement control strategy integrated to a variable structure control scheme (VS¡APPC). In the VS¡APPC, the internal model principle (IMP) of reference currents is used for achieving the zero steady state tracking error of the power system currents. This forces the phase current of the system mains to be sinusoidal with low harmonics content. Moreover, the current controllers are implemented on the stationary reference frame to avoid transformations to the mains voltage vector reference coordinates. This proposed current control strategy enhance the performance of SAPF with fast transient response and robustness to parametric uncertainties. Experimental results are showing for determining the effectiveness of SAPF proposed control system

Simulations of the Frequency Modulated Atomic Force Microscope (FM-AFM) nonlinear control system

The Frequency Modulated - Atomic Force Microscope (FM-AFM) is apowerful tool to perform surface investigation with true atomic resolution. The controlsystem of the FM-AFM must keep constant both the frequency and amplitude ofoscillation of the microcantilever during the scanning process of the sample. However,tip and sample interaction forces cause modulations in the microcantilever motion.A Phase-Locked Loop (PLL) is used as a demodulator and to generate feedback signalto the FM-AFM control system. The PLL performance is vital to the FM-AFMperformace since the image information is in the modulated microcantilever motion.Nevertheless, little attention is drawn to PLL performance in the FM-AFM literature.Here, the FM-AFM control system is simulated, comparing the performancefor di erent PLL designs.

Firmware development and testing for L1/L2 IBL upgrade

Il lavoro di questa tesi riguarda principalmente l'upgrade, la simulazione e il test di schede VME chiamate ReadOut Driver (ROD), che sono parte della catena di elaborazione ed acquisizione dati di IBL (Insertable B-Layer). IBL è il nuovo componente del Pixel Detector dell'esperimento ATLAS al Cern che è stato inserito nel detector durante lo shut down di LHC; fino al 2012 infatti il Pixel Detector era costituito da tre layer, chiamati (partendo dal più interno): Barrel Layer 0, Layer 1 e Layer 2. Tuttavia, l'aumento di luminosità di LHC, l'invecchiamento dei pixel e la richiesta di avere misure sempre più precise, portarono alla necessità di migliorare il rivelatore. Così, a partire dall'inizio del 2013, IBL (che fino a quel momento era stato un progetto sviluppato e finanziato separatamente dal Pixel Detector) è diventato parte del Pixel Detector di ATLAS ed è stato installato tra la beam-pipe e il layer B0. Questa tesi fornirà innanzitutto una panoramica generale dell'esperimento ATLAS al CERN, includendo aspetti sia fisici sia tecnici, poi tratterà in dettaglio le varie parti del rivelatore, con particolare attenzione su Insertable B-Layer. Su quest'ultimo punto la tesi si focalizzerà sui motivi che ne hanno portato alla costruzione, sugli aspetti di design, sulle tecnologie utilizzate (volte a rendere nel miglior modo possibile compatibili IBL e il resto del Pixel Detector) e sulle scelte di sviluppo e fabbricazione. La tesi tratterà poi la catena di read-out dei dati, descrivendo le tecniche di interfacciamento con i chip di front-end, ed in particolare si concentrerà sul lavoro svolto per l'upgrade e lo sviluppo delle schede ReadOut Drivers (ROD) introducendo le migliorie da me apportate, volte a eliminare eventuali difetti, migliorare le prestazioni ed a predisporre il sistema ad una analisi prestazionale del rivelatore. Allo stato attuale le schede sono state prodotte e montate e sono già parte del sistema di acquisizione dati del Pixel Detector di ATLAS, ma il firmware è in continuo aggiornamento. Il mio lavoro si è principalmente focalizzato sul debugging e il miglioramento delle schede ROD; in particolare ho aggiunto due features: - programmazione parallela delle FPGA} delle ROD via VME. IBL richiede l'utilizzo di 15 schede ROD e programmandole tutte insieme (invece che una alla volta) porta ad un sensibile guadagno nei tempi di programmazione. Questo è utile soprattutto in fase di test; - reset del Phase-Locked Loop (PLL)} tramite VME. Il PLL è un chip presente nelle ROD che distribuisce il clock a tutte le componenti della scheda. Avere la possibilità di resettare questo chip da remoto permette di risolvere problemi di sincronizzazione. Le ReadOut Driver saranno inoltre utilizzate da più layer del Pixel Detector. Infatti oltre ad IBL anche i dati provenienti dai layer 1 e 2 dei sensori a pixel dell’esperimento ATLAS verranno acquisiti sfruttando la catena hardware progettata, realizzata e testata a Bologna.

BIDIRECTIONAL AC-DC CONVERTERS USING ONE CYCLE CONTROL (OCC) FOR ELECTRIC VEHICLES

The electric vehicle (EV) market has seen a rapid growth in the recent past. With an increase in the number of electric vehicles on road, there is an increase in the number of high capacity battery banks interfacing the grid. The battery bank of an EV, besides being the fuel tank, is also a huge energy storage unit. Presently, it is used only when the vehicle is being driven and remains idle for rest of the time, rendering it underutilized. Whereas on the other hand, there is a need of large energy storage units in the grid to filter out the fluctuations of supply and demand during a day. EVs can help bridge this gap. The EV battery bank can be used to store the excess energy from the grid to vehicle (G2V) or supply stored energy from the vehicle to grid (V2G ), when required. To let power flow happen, in both directions, a bidirectional AC-DC converter is required. This thesis concentrates on the bidirectional AC-DC converters which have a control on power flow in all four quadrants for the application of EV battery interfacing with the grid. This thesis presents a bidirectional interleaved full bridge converter topology. This helps in increasing the power processing and current handling capability of the converter which makes it suitable for the purpose of EVs. Further, the benefit of using the interleaved topology is that it increases the power density of the converter. This ensures optimization of space usage with the same power handling capacity. The proposed interleaved converter consists of two full bridges. The corresponding gate pulses of each switch, in one cell, are phase shifted by 180 degrees from those of the other cell. The proposed converter control is based on the one-cycle controller. To meet the challenge of new requirements of reactive power handling capabilities for grid connected converters, posed by the utilities, the controller is modified to make it suitable to process the reactive power. A fictitious current derived from the grid voltage is introduced in the controller, which controls the converter performance. The current references are generated using the second order generalized integrators (SOGI) and phase locked loop (PLL). A digital implementation of the proposed control ii scheme is developed and implemented using DSP hardware. The simulated and experimental results, based on the converter topology and control technique discussed here, are presented to show the performance of the proposed theory.

BIDIRECTIONAL AC-DC CONVERTERS USING ONE CYCLE CONTROL (OCC) FOR ELECTRIC VEHICLES

The electric vehicle (EV) market has seen a rapid growth in the recent past. With an increase in the number of electric vehicles on road, there is an increase in the number of high capacity battery banks interfacing the grid. The battery bank of an EV, besides being the fuel tank, is also a huge energy storage unit. Presently, it is used only when the vehicle is being driven and remains idle for rest of the time, rendering it underutilized. Whereas on the other hand, there is a need of large energy storage units in the grid to filter out the fluctuations of supply and demand during a day. EVs can help bridge this gap. The EV battery bank can be used to store the excess energy from the grid to vehicle (G2V) or supply stored energy from the vehicle to grid (V2G ), when required. To let power flow happen, in both directions, a bidirectional AC-DC converter is required. This thesis concentrates on the bidirectional AC-DC converters which have a control on power flow in all four quadrants for the application of EV battery interfacing with the grid. This thesis presents a bidirectional interleaved full bridge converter topology. This helps in increasing the power processing and current handling capability of the converter which makes it suitable for the purpose of EVs. Further, the benefit of using the interleaved topology is that it increases the power density of the converter. This ensures optimization of space usage with the same power handling capacity. The proposed interleaved converter consists of two full bridges. The corresponding gate pulses of each switch, in one cell, are phase shifted by 180 degrees from those of the other cell. The proposed converter control is based on the one-cycle controller. To meet the challenge of new requirements of reactive power handling capabilities for grid connected converters, posed by the utilities, the controller is modified to make it suitable to process the reactive power. A fictitious current derived from the grid voltage is introduced in the controller, which controls the converter performance. The current references are generated using the second order generalized integrators (SOGI) and phase locked loop (PLL). A digital implementation of the proposed control ii scheme is developed and implemented using DSP hardware. The simulated and experimental results, based on the converter topology and control technique discussed here, are presented to show the performance of the proposed theory.

Spectral Signature Secured Retrodirective Array

A novel retrodirective array (RDA) architecture is proposed which utilises a special case spectral signature embedded within the data payload as pilot signals. With the help of a pair of phase-locked-loop (PLL) based phase conjugators (PCs) the RDA’s response to other unwanted and/or unfriendly interrogating signals can be disabled, leading to enhanced secrecy performance directly in the wireless physical layer. The effectiveness of the proposed RDA system is experimentally demonstrated.

Análise e proposição de estratégias de estimação e controle de velocidade para motores de indução trifásicos

This study presents a proposal of speed servomechanisms without the use of mechanical sensors (sensorless) using induction motors. A comparison is performed and propose techniques for pet rotor speed, analyzing performance in different conditions of speed and load. For the determination of control technique, initially, is performed an analysis of the technical literature of the main control and speed estimation used, with their characteristics and limitations. The proposed technique for servo sensorless speed induction motor uses indirect field-oriented control (IFOC), composed of four controllers of the proportional-integral type (PI): rotor flux controller, speed controller and current controllers in the direct and quadrature shaft. As the main focus of the work is in the speed control loop was implemented in Matlab the recursive least squares algorithm (RLS) for identification of mechanical parameters, such as moment of inertia and friction coefficient. Thus, the speed of outer loop controller gains can be self adjusted to compensate for any changes in the mechanical parameters. For speed estimation techniques are analyzed: MRAS by rotóricos fluxes MRAS by counter EMF, MRAS by instantaneous reactive power, slip, locked loop phase (PLL) and sliding mode. A proposition of estimation in sliding mode based on speed, which is performed a change in rotor flux observer structure is displayed. To evaluate the techniques are performed theoretical analyzes in Matlab simulation environment and experimental platform in electrical machinery drives. The DSP TMS320F28069 was used for experimental implementation of speed estimation techniques and check the performance of the same in a wide speed range, including load insertion. From this analysis is carried out to implement closed-loop control of sensorless speed IFOC structure. The results demonstrated the real possibility of replacing mechanical sensors for estimation techniques proposed and analyzed. Among these, the estimator based on PLL demonstrated the best performance in various conditions, while the technique based on sliding mode has good capacity estimation in steady state and robustness to parametric variations.

Design constraints for third-order PLL nodes in master-slave clock distribution networks

Clock signal distribution in telecommunication commercial systems usually adopts a master-slave architecture, with a precise time basis generator as a master and phase-locked loops (PLLs) as slaves. In the majority of the networks, second-order PLLs are adopted due to their simplicity and stability. Nevertheless, in some applications better transient responses are necessary and, consequently, greater order PLLs need to be used, in spite of the possibility of bifurcations and chaotic attractors. Here a master-slave network with third-order PLLs is analyzed and conditions for the stability of the synchronous state are derived, providing design constraints for the node parameters, in order to guarantee stability and reachability of the synchronous state for the whole network. Numerical simulations are carried out in order to confirm the analytical results. (C) 2009 Elsevier B.V. All rights reserved.

Recognition of noisy images by PLL networks

We use networks composed of three phase-locked loops (PLLs), where one of them is the master, for recognizing noisy images. The values of the coupling weights among the PLLs control the noise level which does not affect the successful identification of the input image. Analytical results and numerical tests are presented concerning the scheme performance. (c) 2008 Elsevier B.V. All rights reserved.

Reachability of the synchronous state in a mutually connected PLL network

Second-order phase locked loops (PLLs) are devices that are able to provide synchronization between the nodes in a network even under severe quality restrictions in the signal propagation. Consequently, they are widely used in telecommunication and control. Conventional master-slave (M-S) clock-distribution systems are being, replaced by mutually connected (MC) ones due to their good potential to be used in new types of application such as wireless sensor networks, distributed computation and communication systems. Here, by using an analytical reasoning, a nonlinear algebraic system of equations is proposed to establish the existence conditions for the synchronous state in an MC PLL network. Numerical experiments confirm the analytical results and provide ideas about how the network parameters affect the reachability of the synchronous state. The phase-difference oscillation amplitudes are related to the node parameters helping to design PLL neural networks. Furthermore, estimation of the acquisition time depending on the node parameters allows the performance evaluation of time distribution systems and neural networks based on phase-locked techniques. (c) 2008 Elsevier GmbH. All rights reserved.

Comparative analysis of synchronization algorithms based on PLL, RDFT and Kalman Filter

This paper discusses the main characteristics and presents a comparative analysis of three synchronization algorithms based respectively, on a Phase-Locked Loop, a Kalman Filter and a Discrete Fourier Transform. It will be described the single and three-phase models of the first two methods and the single-phase model of the third one. Details on how to modify the filtering properties or dynamic response of each algorithm will be discussed in terms of their design parameters. In order to compare the different algorithms, these parameters will be set for maximum filter capability. Then, the dynamic response, during input amplitude and frequency deviations will be observed, as well as during the initialization procedure. So, advantages and disadvantages of all considered algorithms will be discussed. ©2007 IEEE.

Implementazione e caratterizzazione di PLL digitali per doppler tracking di sonde deep space

I Phase-Locked Loops sono circuiti ancora oggi utilizzati per la generazione di segnali coerenti in frequenza e in fase con i segnali in ingresso, motivo per cui sono uno degli strumenti della radio scienza per la ricostruzione dei segnali scambiati con le sonde e nascosti dal rumore accumulato nel tragitto che separa le sonde stesse dalle stazioni di tracking a terra. Questa tesi illustra l'implementazione di un PLL digitale linearizzato in Matlab e Simulink in una nuova veste rispetto al modello implementato durante l'attività di tirocinio curricolare, al fine di migliorarne le prestazioni per bassi carrier-to-noise density ratios. Il capitolo 1 si compone di due parti: la prima introduce all'ambito nel quale si inserisce il lavoro proposto, ossia la determinazione d'orbita; la seconda illustra i fondamenti della teoria dei segnali. Il capitolo 2 è incentrato sull'analisi dei Phase-Locked Loops, partendo da un'introduzione teorica e approdando all'implementazione di un modello in Simulink. Il capitolo 3, infine, mostra i risultati dell'applicazione del modello implementato in Simulink nell'analisi dei segnali di una missione realmente svolta.

Network of phase-locking oscillators and a possible model for neural synchronization

In order to model the synchronization of brain signals, a three-node fully-connected network is presented. The nodes are considered to be voltage control oscillator neurons (VCON) allowing to conjecture about how the whole process depends on synaptic gains, free-running frequencies and delays. The VCON, represented by phase-locked loops (PLL), are fully-connected and, as a consequence, an asymptotically stable synchronous state appears. Here, an expression for the synchronous state frequency is derived and the parameter dependence of its stability is discussed. Numerical simulations are performed providing conditions for the use of the derived formulae. Model differential equations are hard to be analytically treated, but some simplifying assumptions combined with simulations provide an alternative formulation for the long-term behavior of the fully-connected VCON network. Regarding this kind of network as models for brain frequency signal processing, with each PLL representing a neuron (VCON), conditions for their synchronization are proposed, considering the different bands of brain activity signals and relating them to synaptic gains, delays and free-running frequencies. For the delta waves, the synchronous state depends strongly on the delays. However, for alpha, beta and theta waves, the free-running individual frequencies determine the synchronous state. (C) 2011 Elsevier B.V. All rights reserved.

Wireless GPS-based phase-locked synchronization system for outdoor environment.

Synchronization of data coming from different sources is of high importance in biomechanics to ensure reliable analyses. This synchronization can either be performed through hardware to obtain perfect matching of data, or post-processed digitally. Hardware synchronization can be achieved using trigger cables connecting different devices in many situations; however, this is often impractical, and sometimes impossible in outdoors situations. The aim of this paper is to describe a wireless system for outdoor use, allowing synchronization of different types of - potentially embedded and moving - devices. In this system, each synchronization device is composed of: (i) a GPS receiver (used as time reference), (ii) a radio transmitter, and (iii) a microcontroller. These components are used to provide synchronized trigger signals at the desired frequency to the measurement device connected. The synchronization devices communicate wirelessly, are very lightweight, battery-operated and thus very easy to set up. They are adaptable to every measurement device equipped with either trigger input or recording channel. The accuracy of the system was validated using an oscilloscope. The mean synchronization error was found to be 0.39 μs and pulses are generated with an accuracy of <2 μs. The system provides synchronization accuracy about two orders of magnitude better than commonly used post-processing methods, and does not suffer from any drift in trigger generation.