Interfaces and traps in pentacene field-effect transistor

The equivalent circuit parameters for a pentacene organic field-effect transistor are determined from low frequency impedance measurements in the dark as well as under light illumination. The source-drain channel impedance parameters are obtained from Bode plot analysis and the deviations at low frequency are mainly due to the contact impedance. The charge accumulation at organic semiconductor-metal interface and dielectric-semiconductor interface is monitored from the response to light as an additional parameter to find out the contributions arising from photovoltaic and photoconductive effects. The shift in threshold voltage is due to the accumulation of photogenerated carriers under source-drain electrodes and at dielectric-semiconductor interface, and also this dominates the carrier transport. The charge carrier trapping at various interfaces and in the semiconductor is estimated from the dc and ac impedance measurements under illumination. (c) 2010 American Institute of Physics. doi: 10.1063/1.3517085]

Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Transfer and detection of single electrons using metal-oxide-semiconductor field-effect transistors

A single-electron turnstile and electrometer circuit was fabricated on a silicon-on-insulator substrate. The turnstile, which is operated by opening and closing two metal-oxide-semiconductor field-effect transistors (MOSFETs) alternately, allows current quantization at 20 K due to single-electron transfer. Another MOSFET is placed at the drain side of the turnstile to form an electron storage island. Therefore, one-by-one electron entrance into the storage island from the turnstile can be detected as an abrupt change in the current of the electrometer, which is placed near the storage island and electrically coupled to it. The correspondence between the quantized current and the single-electron counting was confirmed.

Micropatterning of metal films coated on polymer surfaces with epoxy mold and its application to organic field effect transistor fabrication

In this letter, a simple and versatile approach to micropatterning a metal film, which is evaporated on a Si substrate coated with polymer, is demonstrated by the use of a prepatterned epoxy mold. The polymer interlayer between the metal and the Si substrate is found important for the high quality pattern. When the metal-polymer-Si sandwich structure is heated with the temperature below T-m but above T-g of the polymer, the plastic deformation of the polymer film occurs under sufficiently high pressure applied. It causes the metal to crack locally or weaken along the pattern edges. Further heating while applying a lower pressure results in the formation of an intimate junction between the epoxy stamp and the metal film. Under these conditions the epoxy cures further, ensuring adhesion between the stamp and the film. The lift-off process works because the adhesion between the epoxy and the metal film is stronger than that between the metal film and the polymer. A polymer field effect transistor is fabricated in order to demonstrate potential applications of this micropatterning approach.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Synthesis, characterization and organic field effect transistor performance of a diketopyrrolopyrrole-fluorenone copolymer

A diketopyrrolopyrrole (DPP) with fluorenone (FN) based low band gap alternating copolymer (PDPPT-alt-FN) has been synthesized via Suzuki coupling. PDPPT-alt-FN exhibits a deep HOMO level with a lower band gap. Fabricated organic thin film transistors using PDPPT-alt-FN as a channel semiconductor show p-channel behaviour with the highest hole mobility of 0.083 cm2 V-1 s-1 measured in air.

Density of trap states in a polymer field-effect transistor

We report a more accurate method to determine the density of trap states in a polymer field-effect transistor. In the approach, we describe in this letter, we take into consideration the sub-threshold behavior in the calculation of the density of trap states. This is very important since the sub-threshold regime of operation extends to fairly large gate voltages in these disordered semiconductor based transistors. We employ the sub-threshold drift-limited mobility model (for sub-threshold response) and the conventional linear mobility model for above threshold response. The combined use of these two models allows us to extract the density of states from charge transport data much more accurately. We demonstrate our approach by analyzing data from diketopyrrolopyrrole based co-polymer transistors with high mobility. This approach will also work well for other disordered semiconductors in which sub-threshold conduction is important.

Performance Enhancement of the Tunnel Field Effect Transistor using SiGe Source

Due to extremely low off state current (IOFF) and excellent sub-threshold characteristics, the tunnel field effect transistor (TFET) has attracted a lot of attention for low standby power applications. In this work, we aim to increase the on state current (ION) of the device. A novel device architecture with a SiGe source is proposed. The proposed structure shows an order of improvement in ION compared to the conventional Si structure. A process flow adaptable to conventional CMOS technology is also addressed.

Carbon nanotube Schottky diode and directionally dependent field-effect transistor using asymmetrical contacts

We demonstrate the fabrication and operation of a carbon nanotube (CNT) based Schottky diode by using a Pd contact (high-work-function metal) and an Al contact (low-work-function metal) at the two ends of a single-wall CNT. We show that it is possible to tune the rectification current-voltage (I-V) characteristics of the CNT through the use of a back gate. In contrast to standard back gate field-effect transistors (FET) using same-metal source drain contacts, the asymmetrically contacted CNT operates as a directionally dependent CNT FET when gated. While measuring at source-drain reverse bias, the device displays semiconducting characteristics whereas at forward bias, the device is nonsemiconducting. © 2005 American Institute of Physics.

Piezopotential gated nanowire--nanotube hybrid field-effect transistor.

We report the first piezoelectric potential gated hybrid field-effect transistors based on nanotubes and nanowires. The device consists of single-walled carbon nanotubes (SWNTs) on the bottom and crossed ZnO piezoelectric fine wire (PFW) on the top with an insulating layer between. Here, SWNTs serve as a carrier transport channel, and a single-crystal ZnO PFW acts as the power-free, contact-free gate or even an energy-harvesting component later on. The piezopotential created by an external force in the ZnO PFW is demonstrated to control the charge transport in the SWNT channel located underneath. The magnitude of the piezopotential in the PFW at a tensile strain of 0.05% is measured to be 0.4-0.6 V. The device is a unique coupling between the piezoelectric property of the ZnO PFW and the semiconductor performance of the SWNT with a full utilization of its mobility. The newly demonstrated device has potential applications as a strain sensor, force/pressure monitor, security trigger, and analog-signal touch screen.

Furan containing diketopyrrolopyrrole copolymers : synthesis, characterization, organic field effect transistor performance and photovoltaic properties

In this work, we report design, synthesis and characterization of solution processable low band gap polymer semiconductors, poly{3,6-difuran-2-yl-2,5-di(2- octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-phenylene} (PDPP-FPF), poly{3,6-difuran-2-yl-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1, 4-dione-alt-naphthalene} (PDPP-FNF) and poly{3,6-difuran-2-yl-2,5-di(2- octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-anthracene} (PDPP-FAF) using the furan-containing 3,6-di(furan-2-yl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione (DBF) building block. As DBF acts as an acceptor moiety, a series of donor-acceptor (D-A) copolymers can be generated when it is attached alternatively with phenylene, naphthalene or anthracene donor comonomer blocks. Optical and electrochemical characterization of thin films of these polymers reveals band gaps in the range of 1.55-1.64 eV. These polymers exhibit excellent hole mobility when used as the active layer in organic thin-film transistor (OTFT) devices. Among the series, the highest hole mobility of 0.11 cm 2 V -1 s -1 is achieved in bottom gate and top-contact OTFT devices using PDPP-FNF. When these polymers are used as a donor and [70]PCBM as the acceptor in organic photovoltaic (OPV) devices, power conversion efficiencies (PCE) of 2.5 and 2.6% are obtained for PDPP-FAF and PDPP-FNF polymers, respectively. Such mobility values in OTFTs and performance in OPV make furan-containing DBF a very promising block for designing new polymer semiconductors for a wide range of organic electronic applications.

Fabrication and characterization of polyterpenol as an insulating layer and incorporated organic field effect transistor

A non-synthetic polymer material, polyterpenol, was fabricated using a dry polymerization process namely RF plasma polymerization from an environmentally friendly monomer and its surface, optical and electrical properties investigated. Polyterpenol films were found to be transparent over the visible wavelength range, with a smooth surface with an average roughness of less than 0.4 nm and hardness of 0.4 GPa. The dielectric constant of 3.4 for polyterpenol was higher than that of the conventional polymer materials used in the organic electronic devices. The non-synthetic polymer material was then implemented as a surface modification of the gate insulator in field effect transistor (OFET) and the properties of the device were examined. In comparison to the similar device without the polymer insulating layer, the polyterpenol based OFET device showed significant improvements. The addition of the polyterpenol interlayer in the OFET shifted the threshold voltage significantly; + 20 V to -3 V. The presence of trapped charge was not observed in the polyterpenol interlayer. This assisted in the improvement of effective mobility from 0.012 to 0.021 cm 2/Vs. The switching property of the polyterpenol based OFET was also improved; 107 compared to 104. The results showed that the non-synthetic polyterpenol polymer film is a promising candidate of insulators in electronic devices.