MNEMOSYNE VS MIMESIS, On Memory in Architecture = MNEMOSINE VS MIMESIS, De la memoria en la arquitectura

Memory is an indispensable tool for all architects. An architect without memory is worthless or less than worthless.

Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture

Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of applications, ARM designed the big.LITTLE architecture. This heterogeneous multi-core architecture features two different types of cores: big cores oriented to performance and little cores, slower and aimed to save energy consumption. As all the cores have access to the same memory, multi-threaded applications must resort to some mutual exclusion mechanism to coordinate the access to shared data by the concurrent threads. Transactional Memory (TM) represents an optimistic approach for shared-memory synchronization. To take full advantage of the features offered by software TM, but also benefit from the characteristics of the heterogeneous big.LITTLE architectures, our focus is to propose TM solutions that take into account the power/performance requirements of the application and what it is offered by the architecture. In order to understand the current state-of-the-art and obtain useful information for future power-aware software TM solutions, we have performed an analysis of a popular TM library running on top of an ARM big.LITTLE processor. Experiments show, in general, better scalability for the LITTLE cores for most of the applications except for one, which requires the computing performance that the big cores offer.

On Building a Memory Evolutive System for Application to Learning and Cognition Modeling

We address here aspects of the implementation of a memory evolutive system (MES), based on the model proposed by A. Ehresmann and J. Vanbremeersch (2007), by means of a simulated network of spiking neurons with time dependent plasticity. We point out the advantages and challenges of applying category theory for the representation of cognition, by using the MES architecture. Then we discuss the issues concerning the minimum requirements that an artificial neural network (ANN) should fulfill in order that it would be capable of expressing the categories and mappings between them, underlying the MES. We conclude that a pulsed ANN based on Izhikevich`s formal neuron with STDP (spike time-dependent plasticity) has sufficient dynamical properties to achieve these requirements, provided it can cope with the topological requirements. Finally, we present some perspectives of future research concerning the proposed ANN topology.

An everyday nostalgia: Memory and the fictions of belonging

In 1984, George Orwell presented the future as a dystopian vision, where everyday existence was governed and redefined by an oppressive regime. Winston Smith's daily duties at the Ministry of Truth involved the invention, rewriting and erasing of fragments of history as a means of perpetuating contentment, uniformity and control. History, as Orwell described it in the novel 'was a palimpsest, scraped clean and reinscribed exactly as often as was necessary.' More that a quarter of a century after the publication of 1984, Michel Foucault discussed the cinematic representation and misrepresentation of French history and identity in terms of what he called the manipulation of 'popular memory'. In what was tantamount to a diluted version of Orwell's palimpsestic histories, Foucault stated that 'people are not shown what they were, but what they must remember having been.' This paper will investigate notions of memory, identity and the everyday through a discussion of the community of Celebration in Florida. Conceived in the 1990s, Celebration was designed around a fictionalised representation of pre 1940s small town America, using nostalgia for a mythologised past to create a sense of comfort, community and conformity among its residents. Adapting issues raised by Orwell, Foucault and Baudrillard, this paper will discuss the way in which architecture, like film and literature, can participate in what Foucault discussed as the manipulation of popular memory, inducing and exploiting a nostalgia for an everyday past that that never really existed.

Cognitive intervention protocol for age-related memory impairments

With the number of elderly people increasing tremendously worldwide, comes the need for effective methods to maintain or improve older adults' cognitive performance. Using continuous neurofeedback, through the use of EEG techniques, people can learn how to train and alter their brain electrical activity. A software platform that puts together the proposed rehabilitation methodology has been developed: a digital game protocol that supports neurofeedback training of alpha and theta rhythms, by reading the EEG activity and presenting it back to the subject, interleaved with neurocognitive tasks such as n-Back and Corsi Block-Tapping. This tool will be used as a potential rehabilitative platform for age-related memory impairments.

Write-erase and read paper memory transistor

Applied Physics Letters, Vol.93, issue 20

Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.

Parallel GPU architecture for hyperspectral unmixing based on augmented Lagrangian method

Hyperspectral imaging has become one of the main topics in remote sensing applications, which comprise hundreds of spectral bands at different (almost contiguous) wavelength channels over the same area generating large data volumes comprising several GBs per flight. This high spectral resolution can be used for object detection and for discriminate between different objects based on their spectral characteristics. One of the main problems involved in hyperspectral analysis is the presence of mixed pixels, which arise when the spacial resolution of the sensor is not able to separate spectrally distinct materials. Spectral unmixing is one of the most important task for hyperspectral data exploitation. However, the unmixing algorithms can be computationally very expensive, and even high power consuming, which compromises the use in applications under on-board constraints. In recent years, graphics processing units (GPUs) have evolved into highly parallel and programmable systems. Specifically, several hyperspectral imaging algorithms have shown to be able to benefit from this hardware taking advantage of the extremely high floating-point processing performance, compact size, huge memory bandwidth, and relatively low cost of these units, which make them appealing for onboard data processing. In this paper, we propose a parallel implementation of an augmented Lagragian based method for unsupervised hyperspectral linear unmixing on GPUs using CUDA. The method called simplex identification via split augmented Lagrangian (SISAL) aims to identify the endmembers of a scene, i.e., is able to unmix hyperspectral data sets in which the pure pixel assumption is violated. The efficient implementation of SISAL method presented in this work exploits the GPU architecture at low level, using shared memory and coalesced accesses to memory.

TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs

Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer time-multiplexing and dynamic applications parallelism to enhance device utilization and reduce energy consumption at the cost of additional memory (up to 50% area of the overall platform). To reduce the memory overheads, novel CGRAs employ either statistical compression, intermediate compact representation, or multicasting. Each compaction technique has different properties (i.e. compression ratio, decompression time and decompression energy) and is best suited for a particular class of applications. However, existing research only deals with these methods separately. Moreover, they only analyze the compaction ratio and do not evaluate the associated energy overheads. To tackle these issues, we propose a polymorphic compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to take advantage of a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (up to 52%), decompression energy (up to 4 orders of magnitude), and configuration time (from 33 n to 1.5 s) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.

Non-preemptive and SRP-based fullypreemptive scheduling of real-time Software Transactional Memory

Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. Because of this fact the timing behaviour of the task set may not be predictable, thus it is crucial to limit the execution time overheads resulting from aborts. In this paper we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Then, we propose and evaluate two non-preemptive and one SRP-based fully-preemptive scheduling strategies, in order to avoid transaction starvation.

Crowdsourcing innovation: a proposal for a brokering architecture focused in the innovation needs of SMEs

Crowdsourcing is evolving into powerful outsourcing options for organizations by providing access to the intellectual capital within a vast knowledge community. Innovation brokering services have emerged to facilitate crowdsourcing projects by connecting up companies with potential solution providers within the wider ‘crowd’. Most existing innovation brokering services are primarily aimed at larger organizations, however, Small and Medium Enterprises (SMEs) offer considerable potential for crowdsourcing activity since they are typically the innovation and employment engines in society; they are typically more nimble and responsive to the business environment than the larger companies. SMEs have very different challenges and needs to larger organizations since they have fewer resources, a more limited knowledge and skill base, and immature management practices. Consequently, innovation brokering for SMEs require considerably more support than for larger organizations. This paper identifies the crowdsourcing innovation brokerage facilities needed by SMEs, and presents an architecture that encourages knowledge sharing, development of community, support in mixing and matching capabilities, and management of stakeholders’ risks. Innovation brokering is emerging as a novel business model that is challenging concepts of the traditional value chain and organizational boundaries.

Reconfigurable photonic logic architecture

The amorphous silicon photo-sensor studied in this thesis, is a double pin structure (p(a-SiC:H)-i’(a-SiC:H)-n(a-SiC:H)-p(a-SiC:H)-i(a-Si:H)-n(a-Si:H)) sandwiched between two transparent contacts deposited over transparent glass thus with the possibility of illumination on both sides, responding to wave-lengths from the ultra-violet, visible to the near infrared range. The frontal il-lumination surface, glass side, is used for light signal inputs. Both surfaces are used for optical bias, which changes the dynamic characteristics of the photo-sensor resulting in different outputs for the same input. Experimental studies were made with the photo-sensor to evaluate its applicability in multiplexing and demultiplexing several data communication channels. The digital light sig-nal was defined to implement simple logical operations like the NOT, AND, OR, and complex like the XOR, MAJ, full-adder and memory effect. A pro-grammable pattern emission system was built and also those for the validation and recovery of the obtained signals. This photo-sensor has applications in op-tical communications with several wavelengths, as a wavelength detector and to execute directly logical operations over digital light input signals.

Subjective mental time: the functional architecture of projecting the self to past and future.

Abstract Human experience takes place in the line of mental time (MT) created through 'self-projection' of oneself to different time-points in the past or future. Here we manipulated self-projection in MT not only with respect to one's life events but also with respect to one's faces from different past and future time-points. Behavioural and event-related functional magnetic resonance imaging activity showed three independent effects characterized by (i) similarity between past recollection and future imagination, (ii) facilitation of judgements related to the future as compared with the past, and (iii) facilitation of judgements related to time-points distant from the present. These effects were found with respect to faces and events, and also suggest that brain mechanisms of MT are independent of whether actual life episodes have to be re-experienced or pre-experienced, recruiting a common cerebral network including the anteromedial temporal, posterior parietal, inferior frontal, temporo-parietal and insular cortices. These behavioural and neural data suggest that self-projection in time is a fundamental aspect of MT, relying on neural structures encoding memory, mental imagery and self.

Destruction of lymphoid organ architecture and hepatitis caused by CD4 T cells.

Immune responses have the important function of host defense and protection against pathogens. However, the immune response also causes inflammation and host tissue injury, termed immunopathology. For example, hepatitis B and C virus infection in humans cause immunopathological sequel with destruction of liver cells by the host's own immune response. Similarly, after infection with lymphocytic choriomeningitis virus (LCMV) in mice, the adaptive immune response causes liver cell damage, choriomeningitis and destruction of lymphoid organ architecture. The immunopathological sequel during LCMV infection has been attributed to cytotoxic CD8(+) T cells. However, we now show that during LCMV infection CD4(+) T cells selectively induced the destruction of splenic marginal zone and caused liver cell damage with elevated serum alanin-transferase (ALT) levels. The destruction of the splenic marginal zone by CD4(+) T cells included the reduction of marginal zone B cells, marginal zone macrophages and marginal zone metallophilic macrophages. Functionally, this resulted in an impaired production of neutralizing antibodies against LCMV. Furthermore, CD4(+) T cells reduced B cells with an IgM(high)IgD(low) phenotype (transitional stage 1 and 2, marginal zone B cells), whereas other B cell subtypes such as follicular type 1 and 2 and germinal center/memory B cells were not affected. Adoptive transfer of CD4(+) T cells lacking different important effector cytokines and cytolytic pathways such as IFNγ, TNFα, perforin and Fas-FasL interaction did reveal that these cytolytic pathways are redundant in the induction of immunopathological sequel in spleen. In conclusion, our results define an important role of CD4(+) T cells in the induction of immunopathology in liver and spleen. This includes the CD4(+) T cell mediated destruction of the splenic marginal zone with consecutively impaired protective neutralizing antibody responses.