Solid-state memories based on ferroelectric tunnel junctions.

Ferroic-order parameters are useful as state variables in non-volatile information storage media because they show a hysteretic dependence on their electric or magnetic field. Coupling ferroics with quantum-mechanical tunnelling allows a simple and fast readout of the stored information through the influence of ferroic orders on the tunnel current. For example, data in magnetic random-access memories are stored in the relative alignment of two ferromagnetic electrodes separated by a non-magnetic tunnel barrier, and data readout is accomplished by a tunnel current measurement. However, such devices based on tunnel magnetoresistance typically exhibit OFF/ON ratios of less than 4, and require high powers for write operations (>1 × 10(6) A cm(-2)). Here, we report non-volatile memories with OFF/ON ratios as high as 100 and write powers as low as ∼1 × 10(4) A cm(-2) at room temperature by storing data in the electric polarization direction of a ferroelectric tunnel barrier. The junctions show large, stable, reproducible and reliable tunnel electroresistance, with resistance switching occurring at the coercive voltage of ferroelectric switching. These ferroelectric devices emerge as an alternative to other resistive memories, and have the advantage of not being based on voltage-induced migration of matter at the nanoscale, but on a purely electronic mechanism.

Solid-state memories based on ferroelectric tunnel junctions

Ferroic-order parameters are useful as state variables in non-volatile information storage media because they show a hysteretic dependence on their electric or magnetic field. Coupling ferroics with quantum-mechanical tunnelling allows a simple and fast readout of the stored information through the influence of ferroic orders on the tunnel current. For example, data in magnetic random-access memories are stored in the relative alignment of two ferromagnetic electrodes separated by a non-magnetic tunnel barrier, and data readout is accomplished by a tunnel current measurement. However, such devices based on tunnel magnetoresistance typically exhibit OFF/ON ratios of less than 4, and require high powers for write operations (>1 × 10 6 A cm -2). Here, we report non-volatile memories with OFF/ON ratios as high as 100 and write powers as low as ∼1 × 10 4A cm -2 at room temperature by storing data in the electric polarization direction of a ferroelectric tunnel barrier. The junctions show large, stable, reproducible and reliable tunnel electroresistance, with resistance switching occurring at the coercive voltage of ferroelectric switching. These ferroelectric devices emerge as an alternative to other resistive memories, and have the advantage of not being based on voltage-induced migration of matter at the nanoscale, but on a purely electronic mechanism. © 2012 Macmillan Publishers Limited. All rights reserved.

Magnetic Flip Flops for Space Applications

The radiation environment of space presents a significant threat to the reliability of nonvolatile memory technologies. Ionizing radiation disturbs the charge stored on floating gates, and cosmic rays can permanently damage thin oxides. A new memory technology based on the magnetic tunneling junction (MTJ) appears to offer superior resistance to radiation effects and virtually unlimited write endurance. A magnetic flip flop has a number of potential applications, such as the configuration memory in field-programmable logic devices. However, using MTJs in a flip flop requires radically different circuitry for storing and retrieving data. New techniques are needed to insure that magnetic flip flops are reliable in the radiation environment of space. We propose a new radiation-tolerant magnetic flip flop that uses the inherent resistance of the MTJ to increase its immunity to single event upset and employs a robust “Pac-man” magnetic element.

Performance analysis of AlGaAs/GaAs tunnel junctions for ultra-high concentration photovoltaics

An n(++)-GaAs/p(++)-AlGaAs tunnel junction with a peak current density of 10 100Acm(-2) is developed. This device is a tunnel junction for multijunction solar cells, grown lattice-matched on standard GaAs or Ge substrates, with the highest peak current density ever reported. The voltage drop for a current density equivalent to the operation of the multijunction solar cell up to 10 000 suns is below 5 mV. Trap-assisted tunnelling is proposed to be behind this performance, which cannot be justified by simple band-to-band tunnelling. The metal-organic vapour-phase epitaxy growth conditions, which are in the limits of the transport-limited regime, and the heavy tellurium doping levels are the proposed origins of the defects enabling trap-assisted tunnelling. The hypothesis of trap-assisted tunnelling is supported by the observed annealing behaviour of the tunnel junctions, which cannot be explained in terms of dopant diffusion or passivation. For the integration of these tunnel junctions into a triple-junction solar cell, AlGaAs barrier layers are introduced to suppress the formation of parasitic junctions, but this is found to significantly degrade the performance of the tunnel junctions. However, the annealed tunnel junctions with barrier layers still exhibit a peak current density higher than 2500Acm(-2) and a voltage drop at 10 000 suns of around 20 mV, which are excellent properties for tunnel junctions and mean they can serve as low-loss interconnections in multijunction solar cells working at ultra-high concentrations.

Highly conductive p++-AlGaAs/n ++-GaInP tunnel junctions for ultra-high concentrator solar cells

Tunnel junctions are key for developing multijunction solar cells (MJSC) for ultra-high concentration applications. We have developed a highly conductive, high bandgap p  + + -AlGaAs/n  + + -GaInP tunnel junction with a peak tunneling current density for as-grown and thermal annealed devices of 996 A/cm 2 and 235 A/cm 2, respectively. The J–V characteristics of the tunnel junction after thermal annealing, together with its behavior at MJSCs typical operation temperatures, indicate that this tunnel junction is a suitable candidate for ultra-high concentrator MJSC designs. The benefits of the optical transparency are also assessed for a lattice-matched GaInP/GaInAs/Ge triple junction solar cell, yielding a current density increase in the middle cell of 0.506 mA/cm 2 with respect to previous designs.

Component integration strategies in metamorphic 4-junction III-V concentrator solar cells

Progressing beyond 3-junction inverted-metamorphic multijunction solar cells grown on GaAs substrates, to 4-junction devices, requires the development of high quality metamorphic 0.7 eV GaInAs solar cells. Once accomplished, the integration of this subcell into a full, Monolithic, series connected, 4J-IMM structure demands the development of a metamorphic tunnel junction lattice matched to the 1eV GaInAs subcell. Moreover, the 0.7 eV junction adds about 2 hours of growth time to the structure, implying a heavier annealing of the subcells and tunnel junctions grown first. The final 4J structure is above 20 Pm thick, with about half of this thickness used by the metamorphic buffers required to change the lattice constant throughout the structure. Thinning of these buffers would help reduce the total thickness of the 4J structure to decrease its growth cost and the annealing time. These three topics: development of a metamorphic tunnel junction for the 4th junction, analysis of the annealing, and thinning of the structure, are tackled in this work. The results presented show the successful implementation of an antimonide-based tunnel junction for the 4th junction and of pathways to mitigate the impact of annealing and reduce the thickness of the metamorphic buffers.

Quadruple-junction inverted metamorphic concentrator devices

We present results for quadruple-junction inverted metamorphic (4J-IMM) devices under the concentrated direct spectrum and analyze the present limitations to performance. The devices integrate lattice-matched subcells with rear heterojunctions, as well as lattice-mismatched subcells with low threading dislocation density. To interconnect the subcells, thermally stable lattice-matched tunnel junctions are used, as well as a metamorphic GaAsSb/GaInAs tunnel junction between the lattice-mismatched subcells. A broadband antireflection coating is used, as well as a front metal grid designed for high concentration operation. The best device has a peak efficiency of (43.8 ± 2.2)% at 327-sun concentration, as measured with a spectrally adjustable flash simulator, and maintains an efficiency of (42.9 ± 2.1)% at 869 suns, which is the highest concentration measured. The V_oc increases from 3.445 V at 1-sun to 4.10 V at 327-sun concentration, which indicates high material quality in all of the subcells. The subcell voltages are analyzed using optical modeling, and the present device limitations and pathways to improvement are discussed. Although further improvements are possible, the 4J-IMM structure is clearly capable of very high efficiency at concentration, despite the complications arising from utilizing lattice-mismatched subcells.

Zero-bias conductance and energy gap measurements in LaNiO3-YBa2Cu3O7-x junctions

Conductance measurements of junctions between a high- superconductor and a metallic oxide have been carried out along the a-b plane to examine the tunnel-junction spectra. For these measurements, in situ films have been grown on c-axis oriented thin films using the pulsed laser deposition technique. Two distinctive energy gaps have been observed along with conductance peaks around zero bias. The analysis of zero-bias conductance and energy gap data suggests the presence of midgap states located at the centre of a finite energy gap. The results obtained are also in accordance with the d-wave nature of high- superconductors.

Analysis Of The Energy Quantization Effects On Single Electron Inverter Performance Through Noise Margin Modeling

Possible integration of Single Electron Transistor (SET) with CMOS technology is making the study of semiconductor SET more important than the metallic SET and consequently, the study of energy quantization effects on semiconductor SET devices and circuits is gaining significance. In this paper, for the first time, the effects of energy quantization on SET inverter performance are examined through analytical modeling and Monte Carlo simulations. It is observed that the primary effect of energy quantization is to change the Coulomb Blockade region and drain current of SET devices and as a result affects the noise margin, power dissipation, and the propagation delay of SET inverter. A new model for the noise margin of SET inverter is proposed which includes the energy quantization effects. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. It is shown that SET inverter designed with CT : CG = 1/3 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization.

Modeling and analysis of energy quantization effects on single electron inverter performance

In this paper, for the first time, the effects of energy quantization on single electron transistor (SET) inverter performance are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly changes the Coulomb blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET inverter. A new analytical model for the noise margin of SET inverter is proposed which includes the energy quantization effects. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. A compact expression is developed for a novel parameter quantization threshold which is introduced for the first time in this paper. Quantization threshold explicitly defines the maximum energy quantization that an SET inverter logic circuit can withstand before its noise margin falls below a specified tolerance level. It is found that SET inverter designed with CT:CG=1/3 (where CT and CG are tunnel junction and gate capacitances, respectively) offers maximum robustness against energy quantization.

Assessment of SET Logic Robustness Through Noise Margin Modeling

A compact model for noise margin (NM) of single-electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (zeta). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (CG and CT). It is shown that choosing alpha=CT/CG=1/3 maximizes the NM. An estimate of the maximum tolerable zeta is shown to be equal to plusmn0.03 e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that a isin [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation.

Heteroepitaxy of Group IV and Group III-V semiconductor alloys for photovoltaic applications

Photovoltaic energy conversion represents a economically viable technology for realizing collection of the largest energy resource known to the Earth -- the sun. Energy conversion efficiency is the most leveraging factor in the price of energy derived from this process. This thesis focuses on two routes for high efficiency, low cost devices: first, to use Group IV semiconductor alloy wire array bottom cells and epitaxially grown Group III-V compound semiconductor alloy top cells in a tandem configuration, and second, GaP growth on planar Si for heterojunction and tandem cell applications.

Metal catalyzed vapor-liquid-solid grown microwire arrays are an intriguing alternative for wafer-free Si and SiGe materials which can be removed as flexible membranes. Selected area Cu-catalyzed vapor-liquid solid growth of SiGe microwires is achieved using chlorosilane and chlorogermane precursors. The composition can be tuned up to 12% Ge with a simultaneous decrease in the growth rate from 7 to 1 μm/min^-1. Significant changes to the morphology were observed, including tapering and faceting on the sidewalls and along the lengths of the wires. Characterization of axial and radial cross sections with transmission electron microscopy revealed no evidence of defects at facet corners and edges, and the tapering is shown to be due to in-situ removal of catalyst material during growth. X-ray diffraction and transmission electron microscopy reveal a Ge-rich crystal at the tip of the wires, strongly suggesting that the Ge incorporation is limited by the crystallization rate.

Tandem Ga_1-xIn_xP/Si microwire array solar cells are a route towards a high efficiency, low cost, flexible, wafer-free solar technology. Realizing tandem Group III-V compound semiconductor/Si wire array devices requires optimization of materials growth and device performance. GaP and Ga_1-xIn_xP layers were grown heteroepitaxially with metalorganic chemical vapor deposition on Si microwire array substrates. The layer morphology and crystalline quality have been studied with scanning electron microscopy and transmission electron microscopy, and they provide a baseline for the growth and characterization of a full device stack. Ultimately, the complexity of the substrates and the prevalence of defects resulted in material without detectable photoluminescence, unsuitable for optoelectronic applications.

Coupled full-field optical and device physics simulations of a Ga_0.51In_0.49P/Si wire array tandem are used to predict device performance. A 500 nm thick, highly doped "buffer" layer between the bottom cell and tunnel junction is assumed to harbor a high density of lattice mismatch and heteroepitaxial defects. Under simulated AM1.5G illumination, the device structure explored in this work has a simulated efficiency of 23.84% with realistic top cell SRH lifetimes and surface recombination velocities. The relative insensitivity to surface recombination is likely due to optical generation further away from the free surfaces and interfaces of the device structure.

Finally, GaP has been grown free of antiphase domains on Si (112) oriented substrates using metalorganic chemical vapor deposition. Low temperature pulsed nucleation is followed by high temperature continuous growth, yielding smooth, specular thin films. Atomic force microscopy topography mapping showed very smooth surfaces (4-6 Å RMS roughness) with small depressions in the surface. Thin films (~ 50 nm) were pseudomorphic, as confirmed by high resolution x-ray diffraction reciprocal space mapping, and 200 nm thick films showed full relaxation. Transmission electron microscopy showed no evidence of antiphase domain formation, but there is a population of microtwin and stacking fault defects.

Channel selective tunnelling through a nanographene assembly.

We report selective tunnelling through a nanographene intermolecular tunnel junction achieved via scanning tunnelling microscope tip functionalization with hexa-peri-hexabenzocoronene (HBC) molecules. This leads to an offset in the alignment between the energy levels of the tip and the molecular assembly, resulting in the imaging of a variety of distinct charge density patterns in the HBC assembly, not attainable using a bare metallic tip. Different tunnelling channels can be selected by the application of an electric field in the tunnelling junction, which changes the condition of the HBC on the tip. Density functional theory-based calculations relate the imaged HBC patterns to the calculated molecular orbitals at certain energy levels. These patterns bear a close resemblance to the π-orbital states of the HBC molecule calculated at the relevant energy levels, mainly below the Fermi energy of HBC. This correlation demonstrates the ability of an HBC functionalized tip as regards accessing an energy range that is restricted to the usual operating bias range around the Fermi energy with a normal metallic tip at room temperature. Apart from relating to molecular orbitals, some patterns could also be described in association with the Clar aromatic sextet formula. Our observations may help pave the way towards the possibility of controlling charge transport between organic interfaces.

Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.

The finite bandwidth model for spin fluctuations in Pd

The frequency dependence of the electron-spin fluctuation spectrum, P(Q), is calculated in the finite bandwidth model. We find that for Pd, which has a nearly full d-band, the magnitude, the range, and the peak frequency of P(Q) are greatly reduced from those in the standard spin fluctuation theory. The electron self-energy due to spin fluctuations is calculated within the finite bandwidth model. Vertex corrections are examined, and we find that Migdal's theorem is valid for spin fluctuations in the nearly full band. The conductance of a normal metal-insulator-normal metal tunnel junction is examined when spin fluctuations are present in one electrode. We find that for the nearly full band, the momentum independent self-energy due to spin fluctuations enters the expression for the tunneling conductance with approximately the same weight as the self-energy due to phonons. The effect of spin fluctuations on the tunneling conductance is slight within the finite bandwidth model for Pd. The effect of spin fluctuations on the tunneling conductance of a metal with a less full d-band than Pd may be more pronounced. However, in this case the tunneling conductance is not simply proportional to the self-energy.