Vertical and in-plane electrical transport in InAs/InP semiconductor nanostructures

Vertical and in-plane electrical transport in InAs/InP semiconductors wires and dots have been investigated by conductive atomic force microscopy (C-AFM) and electrical measurements in processed devices. Localized I-V spectroscopy and spatially resolved current images (at constant bias), carried out using C-AFM in a controlled atmosphere at room temperature, show different conductances and threshold voltages for current onset on the two types of nanostructures. The processed devices were used in order to access the in-plane conductance of an assembly with a reduced number of nanostructures. On these devices, signature of two-level random telegraph noise (RTN) in the current behavior with time at constant bias is observed. These levels for electrical current can be associated to electrons removed from the wetting layer and trapped in dots and/or wires. A crossover from conduction through the continuum, associated to the wetting layer, to hopping within the nanostructures is observed with increasing temperature. This transport regime transition is confirmed by a temperature-voltage phase diagram. © 2005 Materials Research Society.

Photodetection with gate-controlled lateral BJTs from standard CMOS technology

The silicon-based gate-controlled lateral bipolar junction transistor (BJT) is a controllable four-terminal photodetector with very high responsivity at low-light intensities. It is a hybrid device composed of a MOSFET, a lateral BJT, and a vertical BJT. Using sufficient gate bias to operate the MOS transistor in inversion mode, the photodetector allows for increasing the photocurrent gain by 106 at low light intensities when the base-emitter voltage is smaller than 0.4 V, and BJT is off. Two operation modes, with constant voltage bias between gate and emitter/source terminals and between gate and base/body terminals, allow for tuning the photoresponse from sublinear to slightly above linear, satisfying the application requirements for wide dynamic range, high-contrast, or linear imaging. MOSFETs from a standard 0.18-μm triple-well complementary-metal oxide semiconductor technology with a width to length ratio of 8 μm /2 μm and a total area of ∼ 500μm2 are used. When using this area, the responsivities are 16-20 kA/W. © 2001-2012 IEEE.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Trench MOS-gated power devices

MOS gated power devices are now available for power switching applications with voltage blocking requirements up to 1 kV and current ratings up to 300A. This is due to the invention of the IGBT, a device in which MOS gate turn-on leads to minority carrier injection to modulate the high resistance drift region required for voltage blocking. The paper presents current technologies being developed in order to expand the applications of MOS gated power devices. Also explained is the available trench gate technology that can be used to fabricate power devices.

Nature of Electronic States in Atomically Thin MoS(2) Field-Effect Transistors

We present low-temperature electrical transport experiments in five field-effect transistor devices consisting of monolayer, bilayer, and trilayer MoS(2) films, mechanically exfoliated onto Si/SiO(2) substrate. Our experiments reveal that the electronic states In all films are localized well up to room temperature over the experimentally accessible range of gate voltage. This manifests in two-dimensional (2D) variable range hopping (VRH) at high temperatures, while below similar to 30 K, the conductivity displays oscillatory structures In gate voltage arising from resonant tunneling at the localized sites. From the correlation energy (T(0)) of VRH and gate voltage dependence of conductivity, we suggest that Coulomb potential from trapped charges In the substrate is the dominant source of disorder in MoS(2) field-effect devices, which leads to carrier localization, as well.

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Critical investigation of high performance spin-coated high-kappa titania thin films based MOS capacitor

We report the tunable dielectric constant of titania films with low leakage current density. Titanium dioxide (TiO2) films of three different thicknesses (36, 63 and 91 nm) were deposited by the consecutive steps of solution preparation, spin-coating, drying, and firing at different temperatures. The problem of poor adhesion between Si substrate and TiO2 insulating layer was resolved by using the plasma activation process. The surface roughness was found to increase with increasing thickness and annealing temperature. The electrical investigation was carried out using metal-oxide-semiconductor structure. The flat band voltage (V-FB), oxide trapped charge (Q(ot)), dielectric constant (kappa) and equivalent oxide thicknesses are calculated from capacitance-voltage (C-V) curves. The C-V characteristics indicate a thickness dependent dielectric constant. The dielectric constant increases from 31 to 78 as thickness increases from 36 to 91 nm. In addition to that the dielectric constant was found to be annealing temperature and frequency dependent. The films having thickness 91 nm and annealed at 600 A degrees C shows the low leakage current density. Our study provides a broad insight of the processing parameters towards the use of titania as high-kappa insulating layer, which might be useful in Si and polymer based flexible devices.

Biologically sensitive field-effect devices using polysilicon TFTs

The authors present a review of recent developments in the detection of biomolecular interactions with field-effect devices. Ion-sensitive field-effect transistors (ISFETs) and enzyme field-effect transistors (EnFETs), based on polycrystalline silicon (poly-Si) TFTs, are discussed. Label-free electrical detection of DNA hybridization has been achieved by a new method, by using MOS capacitors or poly-Si TFTs. In principle, the method can be extended to other chemical or biochemical systems, such as proteins and cells.