Layout plan of area around the workshop "Trud - Schastʻė"

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Layout plan of area around the workshop "Edina prat︠s︡i︠a︡"

Digital image

Document page layout analysis using Harris corner points

Extraction of text areas from the document images with complex content and layout is one of the challenging tasks. Few texture based techniques have already been proposed for extraction of such text blocks. Most of such techniques are greedy for computation time and hence are far from being realizable for real time implementation. In this work, we propose a modification to two of the existing texture based techniques to reduce the computation. This is accomplished with Harris corner detectors. The efficiency of these two textures based algorithms, one based on Gabor filters and other on log-polar wavelet signature, are compared. A combination of Gabor feature based texture classification performed on a smaller set of Harris corner detected points is observed to deliver the accuracy and efficiency.

Circuit layout through an analogy with neural networks

Standard-cell design methodology is an important technique in semicustom-VLSI design. It lends itself to the easy automation of the crucial layout part, and many algorithms have been proposed in recent literature for the efficient placement of standard cells. While many studies have identified the Kerninghan-Lin bipartitioning method as being superior to most others, it must be admitted that the behaviour of the method is erratic, and that it is strongly dependent on the initial partition. This paper proposes a novel algorithm for overcoming some of the deficiencies of the Kernighan-Lin method. The approach is based on an analogy of the placement problem with neural networks, and, by the use of some of the organizing principles of these nets, an attempt is made to improve the behavior of the bipartitioning scheme. The results have been encouraging, and the approach seems to be promising for other NP-complete problems in circuit layout.

Region Based Structure Layout Optimization by Selective Data Copying

As the gap between processor and memory continues to grow Memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to modify an application’s data layout to improve cache locality and cache reuse. Whole program Structure Layout [WPSL] transformations can significantly increase the spatial locality of data and reduce the runtime of programs that use link-based data structures, by increasing the cache line utilization. However, in production compilers WPSL transformations do not realize the entire performance potential possible due to a number of factors. Structure layout decisions made on the basis of whole program aggregated affinity/hotness of structure fields, can be sub optimal for local code regions. WPSL is also restricted in applicability in production compilers for type unsafe languages like C/C++ due to the extensive legality checks and field sensitive pointer analysis required over the entire application. In order to overcome the issues associated with WPSL, we propose Region Based Structure Layout (RBSL) optimization framework, using selective data copying. We describe our RBSL framework, implemented in the production compiler for C/C++ on HP-UX IA-64. We show that acting in complement to the existing and mature WPSL transformation framework in our compiler, RBSL improves application performance in pointer intensive SPEC benchmarks ranging from 3% to 28% over WPSL

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

Pond construction: design and layout of ponds

(4pp.)

Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Experimental evaluation of layout designs for 3 × 3 MIMO-enabled radio-over-fiber distributed antenna systems

This paper experimentally demonstrates that, for two representative indoor distributed antenna system (DAS) scenarios, existing radio-over-fiber (RoF) DAS installations can enhance the capacity advantages of broadband 3 × 3 multiple-input-multiple-output (MIMO) radio services without requiring additional fibers or multiplexing schemes. This is true for both single-and multiple-user cases with a single base station and multiple base stations. First, a theoretical example is used to illustrate that there is a negligible improvement in signal-to-noise ratio (SNR) when using a MIMO DAS with all N spatial streams replicated at N RAUs, compared with a MIMO DAS with only one of the N streams replicated at each RAU for N ≤ 4. It is then experimentally confirmed that a 3 × 3 MIMO DAS offers improved capacity and throughput compared with a 3 × 3 MIMO collocated antenna system (CAS) for the single-user case in two typical indoor DAS scenarios, i.e., one with significant line-of-sight (LOS) propagation and the other with entirely non-line-of-sight (NLOS) propagation. The improvement in capacity is 3.2% and 4.1%, respectively. Then, experimental channel measurements confirm that there is a negligible capacity increase in the 3 × 3 configuration with three spatial streams per antenna unit over the 3 × 3 configuration with a single spatial stream per antenna unit. The former layout is observed to provide an increase of ∼1% in the median channel capacity in both the single-and multiple-user scenarios. With 20 users and three base stations, a MIMO DAS using the latter layout offers median aggregate capacities of 259 and 233 bit/s/Hz for the LOS and NLOS scenarios, respectively. It is concluded that DAS installations can further enhance the capacity offered to multiple users by multiple 3 × 3 MIMO-enabled base stations. Further, designing future DAS systems to support broadband 3 × 3 MIMO systems may not require significant upgrades to existing installations for small numbers of spatial streams. © 2013 IEEE.

A High Performance AlGaN/GaN HEMT with a New Method for T-Gate Layout Design

We propose and fabricate an A1GaN/GaN high electron mobility transistor （HEMT） on sapphire substrate using a new kind of electron beam （EB） lithography layout for the T-gate. Using this new layout,we can change the aspect ratio （ratio of top gate dimension to gate length） and modify the shape of the T-gate freely. Therefore, we obtain a 0.18μm gate-length AlGaN/GaN HEMT with a unity current gain cutoff frequency （f_T） of 65GHz. The aspect ratio of the T-gate is 10. These single finger devices also exhibit a peak extrinsic transconductance of 287mS/mm and a maximum drain current as high as 980mA/mm.

Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

The effects of key geometrical parameters on the performance of integrated spiral inductors are investigated with the 3D electromagnetic simulator HFSS. While varying geometrical parameters such as the number of turns （N）,the width of the metal traces （W）,the spacing between the traces （S）,and the inner diameter （ID）, changes in the performance of the inductors are analyzed in detail. The reasons for these changes in performance are presented. Simulation results indicate that the performance of an integrated spiral inductor can be improved by optimizing its layout. Some design rules are summarized.

Arrayed-Waveguide Layout for AWG Design

于2010-11-23批量导入