Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Fabrication and characterisation of semiconductor nanowires and metal interconnects

One-dimensional semiconductor nanowires are considered to be promising materials for future nanoelectronic applications. However, before these nanowires can be integrated into such applications, a thorough understanding of their growth behaviour is necessary. In particular, methods that allow the control over nanowire growth are deemed especially important as it is these methods that will enable the control of nanowire dimensions such as length and diameter (high aspect ratios). The production of nanowires with high-aspect ratios is vital in order to take advantage of the unique properties experienced at the nanoscale, thus allowing us to maximise their use in devices. Additionally, the development of low-resistivity interconnects is desirable in order to connect such nanowires in multi-nanowire components. Consequently, this thesis aims to discuss the synthesis and characterisation of germanium (Ge) nanowires and platinum (Pt) interconnects. Particular emphasis is placed on manipulating the nanowire growth kinetics to produce high aspect ratio structures. The discussion of Pt interconnects focuses on the development of low-resistivity devices and the electrical and structural analysis of those devices. Chapter 1 reviews the most critical aspects of Ge nanowire growth which must be understood before they can be integrated into future nanodevices. These features include the synthetic methods employed to grow Ge nanowires, the kinetic and thermodynamic aspects of their growth and nanowire morphology control. Chapter 2 outlines the experimental methods used to synthesise and characterise Ge nanowires as well as the methods used to fabricate and analyse Pt interconnects. Chapter 3 discusses the control of Ge nanowire growth kinetics via the manipulation of the supersaturation of Ge in the Au/Ge binary alloy system. This is accomplished through the use of bi-layer films, which pre-form Au/Ge alloy catalysts before the introduction of the Ge precursor. The growth from these catalysts is then compared with Ge nanowire growth from standard elemental Au seeds. Nanowires grown from pre-formed Au/Ge alloy seeds demonstrate longer lengths and higher growth rates than those grown from standard Au seeds. In-situ TEM heating on the Au/Ge bi-layer films is used to support the growth characteristics observed. Chapter 4 extends the work of chapter 3 by utilising Au/Ag/Ge tri-layer films to enhance the growth rates and lengths of Ge nanowires. These nanowires are grown from Au/Ag/Ge ternary alloy catalysts. Once again, the supersaturation is influenced, only this time it is through the simultaneous manipulation of both the solute concentration and equilibrium concentration of Ge in the Au/Ag/Ge ternary alloy system. The introduction of Ag to the Au/Ge binary alloy lowers the equilibrium concentration, thus increasing the nanowire growth rate and length. Nanowires with uniform diameters were obtained via synthesis from AuxAg1-x alloy nanoparticles. Manifestation of the Gibbs-Thomson effect, resulting from the dependence of the mean nanowire length as a function of diameter, was observed for all of the nanowires grown from the AuxAg1-x nanoparticles. Finally, in-situ TEM heating was used to support the nanowire growth characteristics. Chapter 5 details the fabrication and characterisation of Pt interconnects deposited by electron beam induced deposition of two different precursors. The fabrication is conducted inside a dual beam FIB. The electrical and structural characteristics of interconnects deposited from a standard organometallic precursor and a novel carbon-free precursor are compared. The electrical performance of the carbon-free interconnects is shown to be superior to that of the organometallic devices and this is correlated to the structural composition of both interconnects via in-situ TEM heating and HAADF-STEM analysis. Annealing of the interconnects is carried out under two different atmospheres in order to reduce the electrical resistivity even further. Finally, chapter 6 presents some important conclusions and summarises each of the previous chapters.

Novel processes, test structures and characterisation for future germanium technologies

In order to widely use Ge and III-V materials instead of Si in advanced CMOS technology, the process and integration of these materials has to be well established so that their high mobility benefit is not swamped by imperfect manufacturing procedures. In this dissertation number of key bottlenecks in realization of Ge devices are investigated; We address the challenge of the formation of low resistivity contacts on n-type Ge, comparing conventional and advanced rapid thermal annealing (RTA) and laser thermal annealing (LTA) techniques respectively. LTA appears to be a feasible approach for realization of low resistivity contacts with an incredibly sharp germanide-substrate interface and contact resistivity in the order of 10 -7 Ω.cm2. Furthermore the influence of RTA and LTA on dopant activation and leakage current suppression in n+/p Ge junction were compared. Providing very high active carrier concentration > 1020 cm-3, LTA resulted in higher leakage current compared to RTA which provided lower carrier concentration ~1019 cm-3. This is an indication of a trade-off between high activation level and junction leakage current. High ION/IOFF ratio ~ 107 was obtained, which to the best of our knowledge is the best reported value for n-type Ge so far. Simulations were carried out to investigate how target sputtering, dose retention, and damage formation is generated in thin-body semiconductors by means of energetic ion impacts and how they are dependent on the target physical material properties. Solid phase epitaxy studies in wide and thin Ge fins confirmed the formation of twin boundary defects and random nucleation growth, like in Si, but here 600 °C annealing temperature was found to be effective to reduce these defects. Finally, a non-destructive doping technique was successfully implemented to dope Ge nanowires, where nanowire resistivity was reduced by 5 orders of magnitude using PH3 based in-diffusion process.

Nanosize effect in germanium nanowire growth with binary metal alloys

This article describes feasible and improved ways towards enhanced nanowire growth kinetics by reducing the equilibrium solute concentration in the liquid collector phase in a vapor-liquid-solid (VLS) like growth model. Use of bi-metallic alloy seeds (AuxAg1-x) influences the germanium supersaturation for a faster nucleation and growth kinetics. Nanowire growth with ternary eutectic alloys shows Gibbs-Thompson effect with diameter dependent growth rate. In-situ transmission electron microscopy (TEM) annealing experiments directly confirms the role of equilibrium concentration in nanowire growth kinetics and was used to correlate the equilibrium content of metastable alloys with the growth kinetics of Ge nanowires. The shape and geometry of the heterogeneous interfaces between the liquid eutectic and solid Ge nanowires were found to vary as a function of nanowire diameter and eutectic alloy composition.

Disorder induced interface states and their influence on the AI/Ge nanowires Schottky devices

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Resist-substrate interface tailoring for generating high density arrays of Ge and Bi2Se3 nanowires by electron beam lithography

The authors report a chemical process to remove the native oxide on Ge and Bi2Se3 crystals, thus facilitating high-resolution electron beam lithography (EBL) on their surfaces using a hydrogen silsesquioxane (HSQ) resist. HSQ offers the highest resolution of all the commercially available EBL resists. However, aqueous HSQ developers such as NaOH and tetramethylammonium hydroxide have thus far prevented the fabrication of high-resolution structures via the direct application of HSQ to Ge and Bi2Se3, due to the solubility of components of their respective native oxides in these strong aqueous bases. Here we provide a route to the generation of ordered, high-resolution, high-density Ge and Bi2Se3 nanostructures with potential applications in microelectronics, thermoelectric, and photonics devices.                         

AuxAg1-x alloy seeds: A way to control growth, morphology and defect formation in Ge nanowires

Germanium (Ge) nanowires are of current research interest for high speed nanoelectronic devices due to the lower band gap and high carrier mobility compatible with high K-dielectrics and larger excitonic Bohr radius ensuing a more pronounced quantum confinement effect [1-6]. A general way for the growth of Ge nanowires is to use liquid or a solid growth promoters in a bottom-up approach which allow control of the aspect ratio, diameter, and structure of 1D crystals via external parameters, such as precursor feedstock, temperature, operating pressure, precursor flow rate etc [3, 7-11]. The Solid-phase seeding is preferred for more control processing of the nanomaterials and potential suppression of the unintentional incorporation of high dopant concentrations in semiconductor nanowires and unrequired compositional tailing of the seed-nanowire interface [2, 5, 9, 12]. There are therefore distinct features of the solid phase seeding mechanism that potentially offer opportunities for the controlled processing of nanomaterials with new physical properties. A superior control over the growth kinetics of nanowires could be achieved by controlling the inherent growth constraints instead of external parameters which always account for instrumental inaccuracy. The high dopant concentrations in semiconductor nanowires can result from unintentional incorporation of atoms from the metal seed material, as described for the Al catalyzed VLS growth of Si nanowires [13] which can in turn be depressed by solid-phase seeding. In addition, the creation of very sharp interfaces between group IV semiconductor segments has been achieved by solid seeds [14], whereas the traditionally used liquid Au particles often leads to compositional tailing of the interface [15] . Korgel et al. also described the superior size retention of metal seeds in a SFSS nanowire growth process, when compared to a SFLS process using Au colloids [12]. Here in this work we have used silver and alloy seed particle with different compositions to manipulate the growth of nanowires in sub-eutectic regime. The solid seeding approach also gives an opportunity to influence the crystallinity of the nanowires independent of the substrate. Taking advantage of the readily formation of stacking faults in metal nanoparticles, lamellar twins in nanowires could be formed.

Carbon nanotube synthesis from germanium nanoparticles on patterned substrates

Controlled synthesis of carbon nanotubes (CNTs) is highly desirable for nanoelectronic applications. To date, metallic catalyst particles have been deemed unavoidable for the nucleation and growth of any kind of CNTs. Ordered arrays of nanotubes have been obtained by controlled deposition of the metallic catalyst particles. However, the presence of metal species mixed with the CNTs represents a shortcoming for most electronic applications, as metal particles are incompatible with silicon semiconductor technology. In the present paper we report on a metal-catalyst-free synthesis of CNTs, obtained through Ge nanoparticles on a Si(001) surface patterned by nanoindentation. By using acetylene as the carbon feed gas in a low-pressure Chemical Vapor Deposition (CVD) system, multi-walled carbon nanotubes (MWNT) have been observed to arise from the smallest Ge islands. The CNTs and the Ge three-dimensional structures have been analysed by SEM, EDX and AFM in order to assess their elemental features and properties. EDX and SEM results allow confirmation of the absence of any metallic contamination on the surface, indicating that the origin of the CNT growth is due to the Ge nanocrystals.

Towards controlled growth of carbon nanotubes from germanium on nanoindented silicon substrates

In this paper, we report on a metal-catalyst-free synthesis of carbon nanotubes (CNTs) on a pre-patterned Si(001) surface. Arrays of triangular-shaped holes were created by nanoindentation in specific sites of the sample. After germanium deposition and chemical vapor deposition (CVD) of acetylene, a few CNTs nucleated and grew from germanium nanoparticles. These results illustrate that it is possible to control the growth of CNTs without the use of any metal catalyst. By leading the assembly of Ge nanoparticles with a patterning technique, a precise control over the growth order is also attainable.

Controlled carbon nanotube synthesis from germanium nanoparticles

Controlled syntheses of carbon nanotubes (CNTs) are highly desirable for nanoelectronic applications. To date, metallic catalyst particles have usually been deemed unavoidable for the nucleation and growth of any kind of CNTs. However, the presence of metal species mixed with the CNTs represents a shortcoming for most electronic applications, as metal particles are incompatible with silicon semiconductor technology. Recently it has been shown that it is possible to create nanotubes without the presence of metallic catalysts, by using SIO2, Ge and other non-metallic nanoparticles. Here we report on a metal-catalyst-free synthesis of CNTs, obtained through Ge nano-particles assembled on silicon surfaces previously patterned by Focused Ion Beam and nanoindentation.

Molecular dynamics study of dynamic buckling properties of nanowires with defects

Based on the embedded atom method (EAM) and molecular dynamics (MD) method, the deformation properties of Cu nanowires with different single defects under dynamic compression have been studied. The mechanical behaviours of the perfect nanowire are first studied, and the critical stress decreases with the increase of the nanowire’s length, which is well agreed with the modified Euler theory. We then consider the effects to the buckling phenomenon resulted from different defects. It is found that obvious decrease of the critical stress is resulted from different defects, and the largest decrease is found in nanowire with the surface vertical defect. Surface defects are found exerting larger influence than internal defects. The buckling duration is found shortened due to different defects except the nanowire with surface horizon defect, which is also found possessing the largest deflection. Different deflections are also observed for different defected nanowires. It is find that due to surface defects, only deflection in one direction is happened, but for internal defects, more complex deflection circumstances are observed.

Exploration of the defect’s effect on the mechanical properties of different orientated nanowires

Molecular dynamics (MD) simulations have been carried out to investigate the defect’s effect on the mechanical properties of copper nanowire with different crystallographic orientations, under tensile deformation. Three different crystallographic orientations have been considered. The deformation mechanism has been carefully discussed. It is found that the Young’s modulus is insensitive to the defect, even when the nanowire’s crystallographic orientation is different. However, due to the defect’s effect, the yield strength and yield strain appear a large decrease. The defects have played a role of dislocation sources, the slips or stacking faults are first generated around the locations of the defects. The necking locations have also been affected by different defects. Due to the surface defect, the plastic deformation has received a large influence for the <001>/{110} and <110> orientated nanowires, and a relative small influence is seen for the <111> nanowire.

Nanowires of metal oxides for gas sensing applications

Nanowires of different metal oxides (SnO2, ZnO) have been grown by evaporation-condensation process. Their chemical composition has been investigated by using XPS. The standard XPS quantification through main photoelectron peaks, modified Auger parameter and valence band spectra were examined for the accurate determination of oxidation state of metals in the nanowires. Morphological investigation has been conducted by acquiring and analyzing the SEM images. For the simulation of working conditions of sensor, the samples were annealed in ultra high vacuum (UHV) up to 500°C and XPS analysis repeated after this treatment. Finally, the nanowires of SnO 2 have were used to produce a novel gas sensor based on Pt/oxide/SiC structure and operating as Schottky diode. Copyright © 2008 John Wiley & Sons, Ltd.

Numerical exploration of plastic deformation mechanisms of copper nanowires with surface defects

Based on the molecular dynamics simulation, plastic deformation mechanisms associated with the zigzag stress curves in perfect and surface defected copper nanowires under uniaxial tension are studied. In our previous study, it has found that the surface defect exerts larger influence than the centro-plane defect, and the 45o surface defect appears as the most influential surface defect. Hence, in this paper, the nanowire with a 45o surface defect is chosen to investigate the defect’s effect to the plastic deformation mechanism of nanowires. We find that during the plastic deformation of both perfect and defected nanowires, decrease regions of the stress curve are accompanied with stacking faults generation and migration activities, but during stress increase, the structure of the nanowire appears almost unchanged. We also observe that surface defects have obvious influence on the nanowire’s plastic deformation mechanisms. In particular, only two sets of slip planes are found to be active and twins are also observed in the defected nanowire.