Control integrated finite state machine design for photovoltaic module integrated converter

The operation state of photovoltaic Module Integrated Converter (MIC) is subjected to change due to different source and load conditions, while state-swap is usually implemented with flow chart based sequential controller in the past research. In this paper, the signatures for different operational states are evaluated and investigated, which lead to an effective control integrated finite state machine (CIFSM), providing real-time state-swap as fast as the local control loop. The proposed CIFSM is implemented digitally for a boost type MIC prototype and tested under a variety of load and source conditions. The test results prove the effectiveness of the proposed CIFSM design.

On OBDD Transformations Representing Finite State Automata

We present OBDD transformation problem representing finite labeled transition systems corresponding to some congruence relation. Transformations are oriented toward obtaining the OBDD of a minimized transition system for this congruence relation.

Weighted finite-state transducers in speech recognition : a compaction algorithm for non-determinizable transducers

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Weighted finite-state transducers in speech recognition : a compaction algorithm for non-determinizable transducers

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

On prediction of individual sequences

Sequential randomized prediction of an arbitrary binary sequence isinvestigated. No assumption is made on the mechanism of generating the bit sequence. The goal of the predictor is to minimize its relative loss, i.e., to make (almost) as few mistakes as the best ``expert'' in a fixed, possibly infinite, set of experts. We point out a surprising connection between this prediction problem and empirical process theory. First, in the special case of static (memoryless) experts, we completely characterize the minimax relative loss in terms of the maximum of an associated Rademacher process. Then we show general upper and lower bounds on the minimaxrelative loss in terms of the geometry of the class of experts. As main examples, we determine the exact order of magnitude of the minimax relative loss for the class of autoregressive linear predictors and for the class of Markov experts.

Implicit methods for qualitative modeling of gene regulatory networks.

Advancements in high-throughput technologies to measure increasingly complex biological phenomena at the genomic level are rapidly changing the face of biological research from the single-gene single-protein experimental approach to studying the behavior of a gene in the context of the entire genome (and proteome). This shift in research methodologies has resulted in a new field of network biology that deals with modeling cellular behavior in terms of network structures such as signaling pathways and gene regulatory networks. In these networks, different biological entities such as genes, proteins, and metabolites interact with each other, giving rise to a dynamical system. Even though there exists a mature field of dynamical systems theory to model such network structures, some technical challenges are unique to biology such as the inability to measure precise kinetic information on gene-gene or gene-protein interactions and the need to model increasingly large networks comprising thousands of nodes. These challenges have renewed interest in developing new computational techniques for modeling complex biological systems. This chapter presents a modeling framework based on Boolean algebra and finite-state machines that are reminiscent of the approach used for digital circuit synthesis and simulation in the field of very-large-scale integration (VLSI). The proposed formalism enables a common mathematical framework to develop computational techniques for modeling different aspects of the regulatory networks such as steady-state behavior, stochasticity, and gene perturbation experiments.

Reconfigurable Architectures for General-Purpose Computing

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.

Fault Coverage-Driven Incremental Test Generation

In this paper, we consider a classical problem of complete test generation for deterministic finite-state machines (FSMs) in a more general setting. The first generalization is that the number of states in implementation FSMs can even be smaller than that of the specification FSM. Previous work deals only with the case when the implementation FSMs are allowed to have the same number of states as the specification FSM. This generalization provides more options to the test designer: when traditional methods trigger a test explosion for large specification machines, tests with a lower, but yet guaranteed, fault coverage can still be generated. The second generalization is that tests can be generated starting with a user-defined test suite, by incrementally extending it until the desired fault coverage is achieved. Solving the generalized test derivation problem, we formulate sufficient conditions for test suite completeness weaker than the existing ones and use them to elaborate an algorithm that can be used both for extending user-defined test suites to achieve the desired fault coverage and for test generation. We present the experimental results that indicate that the proposed algorithm allows obtaining a trade-off between the length and fault coverage of test suites.

Mapas cognitivos SODA ampliados: prescrição de um método para articular atitudes, comportamentos e seqüências cognitivas a mapas SODA

Este trabalho de tese tem por objetivo ampliar o alcance e aplicação de mapas SODA, preservando a metodologia originalmente desenvolvida. Inicialmente é realizada uma revisão do método, abordando de forma conjunta os artigos seminais, a teoria psicológica de Kelly e a teoria dos grafos; e ao final propomos uma identidade entre construtos de mapas SODA com os conhecimentos tácitos e explícitos, da gestão do conhecimento (KM). Essa sequencia introdutória é completada com uma visão de como os mapas SODA tem sido aplicado. No estágio seguinte o trabalho passa a analisar de forma crítica alguns pontos do método que dão margens a interpretações equivocadas. Sobre elas passamos a propor a aplicação de teorias, de diversos campos, tais como a teoria de means-end (Marketing), a teoria da atribuição e os conceitos de atitude (Psicologia), permitindo inferências que conduzem à proposição da primeira tese: mapas SODA são descritores de atitudes. O próximo estágio prossegue analisando criticamente o método, e foca no paradigma estabelecido por Eden, que não permite conferir ao método o status de descritor de comportamento. Propomos aqui uma mudança de paradigma, adotando a teoria da ação comunicativa, de Habermas, e sobre ela prescrevemos a teoria da ação e da escada da inferência (Action Science) e uma teoria da emoção (neuro ciência), o que permite novas inferências, que conduzem à proposição da segunda tese: mapas SODA podem descrever comportamentos. Essas teses servem de base para o alargamento de escopos do método SODA. É proposta aqui a utilização da teoria de máquinas de estado finito determinístico, designadas por autômato. Demonstramos um mapeamento entre autômato com mapas SODA, obtendo assim o autômato SODA, e sobre ele realizamos a última contribuição, uma proposta de mapas SODA hierárquicos, o que vem a possibilitar a descrição de sequencias de raciocínio, ordenando de forma determinística atitudes e comportamentos, de forma estruturada. A visão de como ela pode ser aplicada é realizada por meio de estudo de caso.

A REACHABILITY TREE FOR STATECHARTS AND ANALYSIS OF SOME PROPERTIES

Statecharts are an extension to finite state machines with capability for expressing hierarchical decomposition and parallelism. They also have a mechanism called history, to remember the last visit to a superstate. An algorithm to create a reachability tree for statecharts is presented. Also shown is how to use this tree to analyse dynamic properties of statecharts; reachability from any state configuration, usage of transitions, reinitiability, deadlocks, and valid sequence of events. Owing to its powerful notation, building a reachability tree for statecharts presents some difficulties, and we show how these problems were solved in the tree we propose.

Ferramentas para a integração de redes de Petri e VHDL na síntese de sistemas digitais

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

On reducing test length for FSMs with extra states

A long-standing problem when testing from a deterministic finite state machine is to guarantee full fault coverage even if the faults introduce extra states in the implementations. It is well known that such tests should include the sequences in a traversal set which contains all input sequences of length defined by the number of extra states. This paper suggests the SPY method, which helps reduce the length of tests by distributing sequences of the traversal set and reducing test branching. It is also demonstrated that an additional assumption about the implementation under test relaxes the requirement of the complete traversal set. The results of the experimental comparison of the proposed method with an existing method indicate that the resulting reduction can reach 40%. Experimental results suggest that the additional assumption about the implementation can help in further reducing the test suite length. Copyright (C) 2011 John Wiley & Sons, Ltd.

MODEL PARTITIONS AND COMPACT TEST CASE SUITES

We present a generalized test case generation method, called the G method. Although inspired by the W method, the G method, in contrast, allows for test case suite generation even in the absence of characterization sets for the specification models. Instead, the G method relies on knowledge about the index of certain equivalences induced at the implementation models. We show that the W method can be derived from the G method as a particular case. Moreover, we discuss some naturally occurring infinite classes of FSM models over which the G method generates test suites that are exponentially more compact than those produced by the W method.

ParTec and KarnUMa-Digital tools as a help for freshman learning

[EN]Freshman students always present lower success rates than other levels of students. Digital systems is a course usually taught at first year studentsand its success rate is not very high. In this work we introduce three digital tools to improve freshman learning designed for easy use and one of them is a tool for mobile terminals that can be used as a game. The first tool is ParTec and is used to implement and test the partition technique. This technique is used to eliminate redundant states in finite state machines. This is a repetitive task that students do not like to perform. The second tool is called KarnUMa and is used for simplifying logic functions through Karnaugh Maps. Simplifying logical functions is a core task for this course and although students usually perform this task better than other tasks, it can still be improved. The third tool is a version of KarnUMa, designed for mobile devices. All the tools are available online for download and have been a helpful tool for students.

A component library to improve the reusability in the development of converged services

The evolution of communications networks to Next Generation Networks (NGN) has encouraged the development of new services. Nowadays, several technologies are being integrated into telecommunications services in order to provide new functionalities, resulting in what are known as converged services. The objective is to adapt the behavior of the services to the necessities of different users, generating customized services. Some of the main technologies involved in their development are those related to the Web. But due to this type of services implies the combination of different technologies, their development is a very complex process that has to be improved to reduce the time and cost required, with the aim of promoting the success of such services. This paper proposes to apply software reuse through the utilization of a component library and presents one focused on ECharts for SIP Servlets (E4SS). It is a framework, based on the SIP Servlet specification, which uses finite state machines for the definition of converged communications services. Also, to promote the use of the library, a methodology is proposed in order to facilitate the integration between the library operations and the software development cycle.