Gigahertz multi-transistor graphene integrated circuits

We review the potential of graphene in ultra-high speed circuits. To date, most of high-frequency graphene circuits typically consist of a single transistor integrated with a few passive components. The development of multi-transistor graphene integrated circuits operating at GHz frequencies can pave the way for applications in which high operating speed is traded off against power consumption and circuit complexity. Novel vertical and planar devices based on a combination of graphene and layered materials could broaden the scope and performances of future devices. © 2013 IEEE.

Whispering-gallery microcavity semiconductor lasers suitable for photonic integrated circuits and optical interconnects

The characteristics of whispering-gallery-like modes in the equilateral triangle and square microresonators are introduced, including directional emission triangle and square microlasers connected to an output waveguide. We propose a photonic interconnect scheme by connecting two directional emission microlasers with an optical waveguide on silicon integrated circuit chip. The measurement indicates that the triangle microlasers can work as a resonance enhanced photodetector for optical interconnect.

Design of two-dimensional photonic crystal edge emitting laser for photonic integrated circuits

An edge emitting laser based on two-dimensional photonic crystal slabs is proposed. The device consists of a square lattice microcavity, which is composed of two structures with the same period but different radius of air-holes, and a waveguide. In the cavity, laser resonance in the inner structure benelits from not only the anomalous dispersion characteristic of the first band-edge at the M point in the first Brillouin-zone but also zero photon states in the outer structure. A line defect waveguide is introduced in the outer structure for extracting photons from the inner cavity. Three-dimensional finite-difference time-domain simulations apparently show the in-plane laser output from the waveguide. The microcavity has an effective mode volume of about 3.2(lambda/eta(slab))(3) for oscillation -mode and the quality factor of the device including line defect waveguide is estimated to be as high as 1300.

Mode analysis of photonic crystal polarization beam splitter and its application in integrated circuits design - art. no. 698437

In this work, the guided modes of a photonic crystal polarization beam splitter (PC-PBS) are studied. We demonstrate that the transmission of a low-loss photonic crystal 120 degrees waveguide bend integrated with the PBS will be influenced if the PBS is multi-moded. We propose a single-moded PC-PBS structure by introducing deformed structures, and it shows twice the enhancement of the transmission. This device with remarkable improvement of performance is promising in the use of photonic crystal integrated circuits design.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

Potential light source for photonic integrated circuits based on the equilateral triangle resonator

The semiconductor microlasers based on the equilateral triangle resonator (ETR) can be fabricated from the edge-emitting laser wafer by dry-etching technique, and the directional emission can be obtained by connecting an output waveguide to one of the vertices of the ETR. We investigate the mode characteristics, especially the mode quality factor, for the ETR with imperfect vertices, which is inevitable in the real technique process. The numerical simulations show that the confined modes can still have a high quality factor in the ETR with imperfect vertices. We can expect that the microlasers is a suitable light source for photonic integrated circuits.

Silicon: the promising material for phontonic integrated circuits platform

The development of optical network demands integrated arid multiple functionality modules to lowing cost and acquire highly reliability. Among the various contender materials to be photonic integrated circuits platform, silicon exhibits dominant characteristics and is the most promising platform materials. The paper compares the characteristics of some candidate materials with silicon and reviews recent progress in silicon based photonic integration technology. Tile challenges to silicon for optical integration for optical networking application arc also indicated.

Systematic delay-driven power optimisation and power-driven delay optimisation of combinational circuits

With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.