Modelling of the time-dependent flow behaviour of lead-free solder pastes used for flip-chip assembly applications

The market for solder paste materials in the electronic manufacturing and assembly sector is very large and consists of material and equipment suppliers and end users. These materials are used to bond electronic components (such as flip-chip, CSP and BGA) to printed circuit boards (PCB's) across a range of dimensions where the solder interconnects can be in the order of 0.05mm to 5mm in size. The non-Newtonian flow properties exhibited by solder pastes during its manufacture and printing/deposition phases have been of practical concern to surface mount engineers and researchers for many years. The printing of paste materials through very small-sized stencil apertures is known to lead to increased stencil clogging and incomplete transfer of paste to the substrate pads. At these very narrow aperture sizes the paste rheology and particle-wall interactions become crucial for consistent paste withdrawal. These non-Newtonian effects must be understood so that the new paste formulations can be optimised for consistent printing. The focus of the study reported in this paper is the characterisation of the rheological properties of solder pastes and flux mediums, and the evaluation of the effect of these properties on the pastes' printing performance at the flip-chip assembly application level. Solder pastes are known to exhibit a thixotropic behaviour, which is recognised by the decrease in apparent viscosity of paste material with time when subjected to a constant shear rate. The proper characterisation of this time-dependent theological behaviour of solder pastes is crucial for establishing the relationships between the pastes' structure and flow behaviour; and for correlating the physical parameters with paste printing performance. In this paper, we present a number of methods which have been developed for characterising the time-dependent and non-Newtonian rheological behaviour of solder pastes and flux mediums as a function of shear rates. We also present results of the study of the rheology of the solder pastes and flux mediums using the structural kinetic modelling approach, which postulates that the network structure of solder pastes breaks down irreversibly under shear, leading to time and shear dependent changes in the flow properties. Our results show that for the solder pastes used in the study, the rate and extent of thixotropy was generally found to increase with increasing shear rate. The technique demonstrated in this study has wide utility for R&D personnel involved in new paste formulation, for implementing quality control procedures used in solder paste manufacture and packaging; and for qualifying new flip-chip assembly lines

Maternal effects on offspring size and packaging constraints in the whelk

Life-history theory predicts an optimal offspring size, irrespective of reproductive effort; however, in some species offspring size correlates positively with maternal size. We examine hypotheses for why this latter situation should occur in the whelk Buccinum undatum. The trade-offs between aspects of reproduction in whelks are complicated due to the provision of protective egg capsules. Many eggs are placed within each capsule but c. 99% of these eggs are consumed by the remaining developing young. Large maternal size results in more eggs, larger eggs, more eggs consumed per hatchling, more capsules, larger capsules, more eggs per capsule, a larger number of hatchlings per capsule and larger hatchlings. Increased intra-capsule and post-hatch sibling competition may decrease the marginal value for additional young and select for larger young, however, our data do not support this explanation. Instead, packaging constraints within each capsule limit the size of hatchlings but this constraint is relaxed for medium to large females because they produce large capsules. Small females appear to produce young below optimum size because of the space constraint thus explaining the correlation between maternal size and offspring size.

Label-free isolation of a prostate cancer cell among blood cells and the single-cell measurement of drug accumulation using an integrated microfluidic chip

Circulating tumor cells (CTCs) are found in the blood of patients with cancer. Although these cells are rare, they can provide useful information for chemotherapy. However, isolation of these rare cells from blood is technically challenging because they are small in numbers. An integrated microfluidic chip, dubbed as CTC chip, was designed and fabricated for conducting tumor cell isolation. As CTCs usually show multidrug resistance (MDR), the effect of MDR inhibitors on chemotherapeutic drug accumulation in the isolated single tumor cell is measured. As a model of CTC isolation, human prostate tumor cells were mixed with mouse blood cells and the labelfree isolation of the tumor cells was conducted based on cell size difference. The major advantages of the CTC chip are the ability for fast cell isolation, followed by multiple rounds of single-cell measurements, suggesting a potential assay for detecting the drug responses based on the liquid biopsy of cancer patients.

Influence of tool rake angle on the quality of pure magnesium chip-consolidated product

Chips were produced by orthogonal Cutting of cast pure magnesium billet with three different tool rake angles viz., -15 degrees, -5 degrees and +15 degrees on a lathe. Chip consolidation by solid state recycling technique involved cold compaction followed by hot extrusion. The extruded products were characterized for microstructure and mechanical properties. Chip-consolidated products from -15 degrees rake angle tools showed 19% increase in tensile strength, 60% reduction ingrain size and 12% increase in hardness compared to +15 degrees rake chip-consolidated product indicating better chip bonding and grain refinement. Microstructure of the fracture specimen Supports the abovefinding. On the overall, the present work high lights the importance of tool take angle in determining the quality of the chip-consolidated products. (C) 2009 Elsevier B.V. All rights reserved.

Electro-magnetically Actuated Minute Polymer Pump Fabricated using Packaging Technology

Design, fabrication and preliminary testing of a flat pump with millimetre thickness are described in this paper. The pump is entirely made of polymer materials barring the magnet and copper coils used for electromagnetic actuation. The fabrication is carried out using widely available microelectronic packaging machinery and techniques. Therefore, the fabrication of the pump is straightforward and inexpensive. Two types of prototypes are designed and built. One consists of copper coils that are etched on an epoxy plate and the other has wound insulated wire of 90 mu m diameter to serve as a coil. The overall size of the first pump is 25 mm x 25 mm x 3.6 mm including the 3.1 mm-thick NdFeB magnet of diameter 12 mm. It consists of a pump chamber of 20 mm x 20 mm x 0.8 mm with copper coils etched from a copper-clad epoxy plate using dry-film lithography and milled using a CNC milling machine, two passive valves and the pump-diaphragm made of Kapton film of 0.089 mm thickness. The second pump has an overall size of 35 mm x 35 mm x 4.4 mm including the magnet and the windings. A breadboard circuit and DC power supply are used to test the pump by applying an alternating square-wave voltage pulse. A water slug in a tube attached to the inlet is used to observe and measure the air-flow induced by the pump against atmospheric pressure. The maximum flow rate was found to be 15 ml/min for a voltage of 2.5 V and a current of 19 mA at 68 Hz.

Analysis of integrated optofluidic lab-on-a-chip fluorescence biosensor based on transmittance of light through a fluidic gap

Sensitivity analysis is an important aspect to be looked into while designing lab-on-a-chip systems. In this paper we will be showing with appropriate design that the best sensitivity of the fluorescence biosensor is achieved for an optimal width of fluidic gap, corresponding to a particular mode spot size. We will be also showing that the sensitivity of the biosensor is affected by efficiency of light coupling, which is influenced by changes in the width of fluidic gap, refractive index of the fluid and higher order modes.

Microstructure and compression behavior of chip consolidated magnesium

Chips produced by turning a commercial purity magnesium billet were cold compacted and then hot extruded at four different temperatures: 250, 300, 350, and 400 degrees C. Cast billets, of identical composition, were also extruded as reference material. Chip boundaries, visible even after 49: 1 extrusion at 400 degrees C, were observed to suppress grain coarsening. Although 250 degrees C extruded chip-consolidated product showed early onset of yielding and lower ductility, fully dense material (extruded at 400 degrees C) had nearly 40% reduction in grain size with 22% higher yield strength and comparable ductility as that of the reference. The study highlights the role of densification and grain refinement on the compression behavior of chip consolidated specimens.

Adaptive power optimization of on-chip SNUCA cache on tiled chip multicore architecture using remap policy

Advances in technology have increased the number of cores and size of caches present on chip multicore platforms(CMPs). As a result, leakage power consumption of on-chip caches has already become a major power consuming component of the memory subsystem. We propose to reduce leakage power consumption in static nonuniform cache architecture(SNUCA) on a tiled CMP by dynamically varying the number of cache slices used and switching off unused cache slices. A cache slice in a tile includes all cache banks present in that tile. Switched-off cache slices are remapped considering the communication costs to reduce cache usage with minimal impact on execution time. This saves leakage power consumption in switched-off L2 cache slices. On an average, there map policy achieves 41% and 49% higher EDP savings compared to static and dynamic NUCA (DNUCA) cache policies on a scalable tiled CMP, respectively.

Analysis of integrated optofluidic lab-on-a-chip sensor based on refractive index and absorbance sensing

The analysis of a fully integrated optofluidic lab-on-a-chip sensor is presented in this paper. This device is comprised of collinear input and output waveguides that are separated by a microfluidic channel. When light is passed through the analyte contained in the fluidic gap, optical power loss occurs owing to absorption of light. Apart from absorption, a mode-mismatch between the input and output waveguides occurs when the light propagates through the fluidic gap. The degree of mode-mismatch and quantum of optical power loss due to absorption of light by the fluid form the basis of our analysis. This sensor can detect changes in refractive index and changes in concentration of species contained in the analyte. The sensitivity to detect minute changes depends on many parameters. The parameters that influence the sensitivity of the sensor are mode spot size, refractive index of the fluid, molar concentration of the species contained in the analyte, width of the fluidic gap, and waveguide geometry. By correlating various parameters, an optimal fluidic gap distance corresponding to a particular mode spot size that achieves the best sensitivity is determined both for refractive index and absorbance-based sensing.

Dense, efficient chip-to-chip communication at the extremes of computing

The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Communication is a necessary adjunct to computation, and whether this is to push data from node-to-node in a high-performance computing cluster or from the receiver of wireless link to a neural stimulator in a biomedical implant, interconnect can take up a significant portion of the overall system power budget. Although a single interconnect methodology cannot address such a broad range of systems efficiently, there are a number of key design concepts that enable good interconnect design in the age of highly-scaled CMOS: an emphasis on highly-digital approaches to solving ‘analog’ problems, hardware sharing between links as well as between different functions (such as equalization and synchronization) in the same link, and adaptive hardware that changes its operating parameters to mitigate not only variation in the fabrication of the link, but also link conditions that change over time. These concepts are demonstrated through the use of two design examples, at the extremes of the power and performance spectra.

A novel all-digital clock and data recovery technique for high-performance, high density interconnect has been developed. Two independently adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase is placed in the middle of the eye to recover the data, while the other is swept across the delay line. The samples produced by the two clocks are compared to generate eye information, which is used to determine the best phase for data recovery. The functions of the two clocks are swapped after the data phase is updated; this ping-pong action allows an infinite delay range without the use of a PLL or DLL. The scheme's generalized sampling and retiming architecture is used in a sharing technique that saves power and area in high-density interconnect. The eye information generated is also useful for tuning an adaptive equalizer, circumventing the need for dedicated adaptation hardware.

On the other side of the performance/power spectra, a capacitive proximity interconnect has been developed to support 3D integration of biomedical implants. In order to integrate more functionality while staying within size limits, implant electronics can be embedded onto a foldable parylene (‘origami’) substrate. Many of the ICs in an origami implant will be placed face-to-face with each other, so wireless proximity interconnect can be used to increase communication density while decreasing implant size, as well as facilitate a modular approach to implant design, where pre-fabricated parylene-and-IC modules are assembled together on-demand to make custom implants. Such an interconnect needs to be able to sense and adapt to changes in alignment. The proposed array uses a TDC-like structure to realize both communication and alignment sensing within the same set of plates, increasing communication density and eliminating the need to infer link quality from a separate alignment block. In order to distinguish the communication plates from the nearby ground plane, a stimulus is applied to the transmitter plate, which is rectified at the receiver to bias a delay generation block. This delay is in turn converted into a digital word using a TDC, providing alignment information.

A packaging technique for silicon MEMS strain sensors on steel

A packaging technique suited to applying MEMS strain sensors realized on a silicon chip to a steel flat surface is described. The method is based on adhesive bonding of the silicon chip rear surface on steel using two types of glue normally used for standard piezoresistive strain sensors (Mbond200/ 600), using direct wire bonding of the chip to a Printed Circuit Board, also fixed on steel. In order to protect the sensor from the external environment, and to improve the MEMS performance, the silicon chip is encapsulated with a metal cap hermetically sealed-off under vacuum condition with a vacuum adhesive in which the bonding wires are also protected from possible damage. In order to evaluate the mechanical coupling of the silicon chip with the bar and thestress transfer extent to the silicon surface, commercial strain sensors have been applied on the chip glued on a steel bar in alaboratory setup able to generate strain by inflection, yielding a stress transfer around 70% from steel to silicon. © 2008 IEEE.

Subwavelength plasmonics for graded-index optics on a chip.

Planar plasmonic devices are becoming attractive for myriad applications, owing to their potential compatibility with standard microelectronics technology and the capability for densely integrating a large variety of plasmonic devices on a chip. Mitigating the challenges of using plasmonics in on-chip configurations requires precise control over the properties of plasmonic modes, in particular their shape and size. Here we achieve this goal by demonstrating a planar plasmonic graded-index lens focusing surface plasmons propagating along the device. The plasmonic mode is manipulated by carving subwavelength features into a dielectric layer positioned on top of a uniform metal film, allowing the local effective index of the plasmonic mode to be controlled using a single binary lithographic step. Focusing and divergence of surface plasmons is demonstrated experimentally. The demonstrated approach can be used for manipulating the propagation of surface plasmons, e.g., for beam steering, splitting, cloaking, mode matching, and beam shaping applications.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

High-frequency characterization of packaging network in to-can photodiode modules

A simple method for analyzing the effects of TO packaging network on the high-frequency response of photodiode modules is presented. This method is established based on the relations of the scattering parameters of the packaging network, photodiode chip, and module. It is shown that the results obtained by this method agree well with those obtained by the conventional comparison method. The proposed method is much more convenient since only the electrical domain measurements are required. (C) 2008 Wiley Periodicals, Inc.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.