Desenvolvimento de um processador VLIW

Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e Computadores

Escritas da utopia na literatura contemporânea – da utopia à distopia

Tese de Doutoramento em Ciências da Literatura (Especialidade em Literatura Comparada)

The influence of the Palestinian sociocultural values in shaping the vernacular architecture of Nablus city

Recently, environmental architecture and sustainable construction has been ranked on top of the worldâ s interests. Making use of natural resources helps in reducing energy consumption and costs associated with the operation of buildings. The current architectural approaches and designs in Palestine are far away from environmental concepts, copying and simulating abroad approaches, without taking into account the culture, climate, and inhabitant's needs. On the contrast, vernacular architecture has achieved environmental concepts and has given suitable approaches and samples - without any need to simulate or copy - which come from people and land. This paper discusses how the Palestinian socio-cultural context shaped the residential vernacular architecture in Palestine, taking the old city of Nablus as a case-study. The research concept depends on analysing and trying to understand the effect of the socio-cultural context on vernacular architecture and trying to reach some rules or understandings of how it works in order to reach a modern environmental dwelling that is suitable to this concept. The research method goes through analysing study cases from the traditional architecture models and the Nablus city is selected as a case study. This analytical and qualitative method can lead to deep understanding for how to benefit from vernacular architecture in Palestine in finding the future environmental residential construction. One of the main findings of this research is to set general and special rules for building sustainable buildings in Palestine from the socio-cultural point view, in order to be a reference for designers, stakeholders, ministry of planning, and municipalities.

Utilização de computação de elevado desempenho para a simulação de problemas de hidrodinâmica costeira

Dissertação de mestrado integrado em Engenharia Civil

Upgrade of an industrial building: BIM model of the as-built situation and evaluation of modifications

Dissertação de mestrado integrado in Civil Engineering

A modular traffic sampling architecture for flexible network measurements

Dissertação de Mestrado (Programa Doutoral em Informática)

Towards a pervasive data mining engine: architecture overview

Current data mining engines are difficult to use, requiring optimizations by data mining experts in order to provide optimal results. To solve this problem a new concept was devised, by maintaining the functionality of current data mining tools and adding pervasive characteristics such as invisibility and ubiquity which focus on their users, providing better ease of use and usefulness, by providing autonomous and intelligent data mining processes. This article introduces an architecture to implement a data mining engine, composed by four major components: database; Middleware (control); Middleware (processing); and interface. These components are interlinked but provide independent scaling, allowing for a system that adapts to the user’s needs. A prototype has been developed in order to test the architecture. The results are very promising and showed their functionality and the need for further improvements.

An illustrated flora of the northern United States, Canada and the British possessions : from Newfoundland to the parallel of the southern boundary of Virginia, and from the Atlantic Ocean westward to the 102d meridian / by Nathaniel Lord Britton and Hon. Addison Brown.

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Aceleración de Algoritmos en Procesadores Multicore, GPGPU y FPGA. Algorithm Acceleration with Multicore, GPGPU and FPGA Processors.

El avance en la potencia de cómputo en nuestros días viene dado por la paralelización del procesamiento, dadas las características que disponen las nuevas arquitecturas de hardware. Utilizar convenientemente este hardware impacta en la aceleración de los algoritmos en ejecución (programas). Sin embargo, convertir de forma adecuada el algoritmo en su forma paralela es complejo, y a su vez, esta forma, es específica para cada tipo de hardware paralelo. En la actualidad los procesadores de uso general más comunes son los multicore, procesadores paralelos, también denominados Symmetric Multi-Processors (SMP). Hoy en día es difícil hallar un procesador para computadoras de escritorio que no tengan algún tipo de paralelismo del caracterizado por los SMP, siendo la tendencia de desarrollo, que cada día nos encontremos con procesadores con mayor numero de cores disponibles. Por otro lado, los dispositivos de procesamiento de video (Graphics Processor Units - GPU), a su vez, han ido desarrollando su potencia de cómputo por medio de disponer de múltiples unidades de procesamiento dentro de su composición electrónica, a tal punto que en la actualidad no es difícil encontrar placas de GPU con capacidad de 200 a 400 hilos de procesamiento paralelo. Estos procesadores son muy veloces y específicos para la tarea que fueron desarrollados, principalmente el procesamiento de video. Sin embargo, como este tipo de procesadores tiene muchos puntos en común con el procesamiento científico, estos dispositivos han ido reorientándose con el nombre de General Processing Graphics Processor Unit (GPGPU). A diferencia de los procesadores SMP señalados anteriormente, las GPGPU no son de propósito general y tienen sus complicaciones para uso general debido al límite en la cantidad de memoria que cada placa puede disponer y al tipo de procesamiento paralelo que debe realizar para poder ser productiva su utilización. Los dispositivos de lógica programable, FPGA, son dispositivos capaces de realizar grandes cantidades de operaciones en paralelo, por lo que pueden ser usados para la implementación de algoritmos específicos, aprovechando el paralelismo que estas ofrecen. Su inconveniente viene derivado de la complejidad para la programación y el testing del algoritmo instanciado en el dispositivo. Ante esta diversidad de procesadores paralelos, el objetivo de nuestro trabajo está enfocado en analizar las características especificas que cada uno de estos tienen, y su impacto en la estructura de los algoritmos para que su utilización pueda obtener rendimientos de procesamiento acordes al número de recursos utilizados y combinarlos de forma tal que su complementación sea benéfica. Específicamente, partiendo desde las características del hardware, determinar las propiedades que el algoritmo paralelo debe tener para poder ser acelerado. Las características de los algoritmos paralelos determinará a su vez cuál de estos nuevos tipos de hardware son los mas adecuados para su instanciación. En particular serán tenidos en cuenta el nivel de dependencia de datos, la necesidad de realizar sincronizaciones durante el procesamiento paralelo, el tamaño de datos a procesar y la complejidad de la programación paralela en cada tipo de hardware. Today´s advances in high-performance computing are driven by parallel processing capabilities of available hardware architectures. These architectures enable the acceleration of algorithms when thes ealgorithms are properly parallelized and exploit the specific processing power of the underneath architecture. Most current processors are targeted for general pruposes and integrate several processor cores on a single chip, resulting in what is known as a Symmetric Multiprocessing (SMP) unit. Nowadays even desktop computers make use of multicore processors. Meanwhile, the industry trend is to increase the number of integrated rocessor cores as technology matures. On the other hand, Graphics Processor Units (GPU), originally designed to handle only video processing, have emerged as interesting alternatives to implement algorithm acceleration. Current available GPUs are able to implement from 200 to 400 threads for parallel processing. Scientific computing can be implemented in these hardware thanks to the programability of new GPUs that have been denoted as General Processing Graphics Processor Units (GPGPU).However, GPGPU offer little memory with respect to that available for general-prupose processors; thus, the implementation of algorithms need to be addressed carefully. Finally, Field Programmable Gate Arrays (FPGA) are programmable devices which can implement hardware logic with low latency, high parallelism and deep pipelines. Thes devices can be used to implement specific algorithms that need to run at very high speeds. However, their programmability is harder that software approaches and debugging is typically time-consuming. In this context where several alternatives for speeding up algorithms are available, our work aims at determining the main features of thes architectures and developing the required know-how to accelerate algorithm execution on them. We look at identifying those algorithms that may fit better on a given architecture as well as compleme

An illustrated flora of the northern United States, Canada and the British possessions : from Newfoundland to the parallel of the southern boundary of Virginia, and from the Atlantic Ocean westward to the 102d meridian / by Nathaniel Lord Britton and Hon. Addison Brown.

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An illustrated flora of the northern United States, Canada and the British possessions : from Newfoundland to the parallel of the southern boundary of Virginia, and from the Atlantic Ocean westward to the 102d meridian / by Nathaniel Lord Britton and Hon. Addison Brown.

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The shoulder architecture of bears and other carnivores [by] D. Dwight Davis.

v.31:no.34(1949)

Cellular DBMS : customizable and autonomous data management using a RISC-style architecture

Magdeburg, Univ., Fak. für Informatik, Diss., 2011

Direct numerical simulation of turbulent flames on parallel computers

Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2012

Simulation of lime calcination in normal shaft an parallel flow regenerative kilns

Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2012