Modelling and Control of Shape Memory Alloy Actuators by using Preisach Model, Genetic Algorithm and Fuzzy Logic

Shapememoryalloy (SMA) actuators, which have the ability to return to a predetermined shape when heated, have many potential applications in aeronautics, surgical tools, robotics and so on. Nonlinearity hysteresis effects existing in SMA actuators present a problem in the motion control of these smart actuators. This paper investigates the control problem of SMA actuators in both simulation and experiment. In the simulation, the numerical Preisachmodel with geometrical interpretation is used for hysteresis modeling of SMA actuators. This model is then incorporated in a closed loop PID control strategy. The optimal values of PID parameters are determined by using geneticalgorithm to minimize the mean squared error between desired output displacement and simulated output. However, the control performance is not good compared with the simulation results when these parameters are applied to the real SMA control since the system is disturbed by unknown factors and changes in the surrounding environment of the system. A further automated readjustment of the PID parameters using fuzzylogic is proposed for compensating the limitation. To demonstrate the effectiveness of the proposed controller, real time control experiment results are presented.

Improvement of the Performance of Hysteresis Compensation in SMA Actuators by Using Inverse Preisach Model in Closed – Loop Control System

The aim of this paper is to increase the performance of hysteresis compensation for Shape Memory Alloy (SMA) actuators by using inverse Preisach model in closed — loop control system. This is used to reduce hysteresis effects and improve accuracy for the displacement of SMA actuators. Firstly, hysteresis is identified by numerical Preisach model implementation. The geometrical interpretation from first order transition curves is used for hysteresis modeling. Secondly, the inverse Preisach model is formulated and incorporated in closed-loop PID control system in order to obtain desired current-to-displacement relationship with hysteresis reducing. The experimental results for hysteresis compensation by using this method are also shown in this paper.

Predictive position and force control for shape memory alloy cylinders

In this paper, a linear lightweight electric cylinder constructed using shape memory alloy (SMA) is proposed. Spring SMA is used as the actuator to control the position and force of the cylinder rod. The model predictive control algorithm is investigated to compensate SMA hysteresis phenomenon and control the cylinder. In the predictive algorithm, the future output of the cylinder is computed based on the cylinder model, and the control signal is computed to minimize the error and power criterion. The cylinder model parameters are estimated by an online identification algorithm. Experimental results show that the SMA cylinder is able to precisely control position and force by using the predictive control strategy though the hysteresis effect existing in the actuator. The performance of the proposed controller is compared with that of a conventional PID controller

Valved Dataflow For FPGA Memory Hierarchy Synthesis

For modern FPGA, implementation of memory intensive processing applications such as high end image and video processing systems necessitates manual design of complex multilevel memory hierarchies incorporating off-chip DDR and onchip BRAM and LUT RAM. In fact, automated synthesis of multi-level memory hierarchies is an open problem facing high level synthesis technologies for FPGA devices. In this paper we describe the first automated solution to this problem.
By exploiting a novel dataflow application modelling dialect, known as Valved Dataflow, we show for the first time how, not only can such architectures be automatically derived, but also that the resulting implementations support real-time processing for current image processing application standards such as H.264. We demonstrate the viability of this approach by reporting the performance and cost of hierarchies automatically generated for Motion Estimation, Matrix Multiplication and Sobel Edge Detection applications on Virtex-5 FPGA.

Automatic FPGA Synthesis of Memory Intensive C-based Kernels

Realising high performance image and signal processing
applications on modern FPGA presents a challenging implementation problem due to the large data frames streaming through these systems. Specifically, to meet the high bandwidth and data storage demands of these applications, complex hierarchical memory architectures must be manually specified
at the Register Transfer Level (RTL). Automated approaches which convert high-level operation descriptions, for instance in the form of C programs, to an FPGA architecture, are unable to automatically realise such architectures. This paper
presents a solution to this problem. It presents a compiler to automatically derive such memory architectures from a C program. By transforming the input C program to a unique dataflow modelling dialect, known as Valved Dataflow (VDF), a mapping and synthesis approach developed for this dialect can
be exploited to automatically create high performance image and video processing architectures. Memory intensive C kernels for Motion Estimation (CIF Frames at 30 fps), Matrix Multiplication (128x128 @ 500 iter/sec) and Sobel Edge Detection (720p @ 30 fps), which are unrealisable by current state-of-the-art C-based synthesis tools, are automatically derived from a C description of the algorithm.

Reduced-memory multirate vector quantisation

A new method is proposed which reduces the size of the memory needed to implement multirate vector quantizers. Investigations have shown that the performance of the coders implemented using this approach is comparable to that obtained from standard systems. The proposed method can therefore be used to reduce the hardware required to implement real-time speech coders.

High performance IP lookup circuit using DDR SDRAM

DDR-SDRAM based data lookup techniques are evolving into a core technology for packet lookup applications for data network, benefitting from the features of high density, high bandwidth and low price of DDR memory products in the market. Our proposed DDR-SDRAM based lookup circuit is capable of achieving IP header lookup for network line-rates of up to 10Gbps, providing a solution on high-performance and economic packet header inspections. ©2008 IEEE.

Episodic memory and learning in patients with chronic schizophrenia

This study explored the pattern of memory functioning in 58 patients with chronic schizophrenia and compared their performance with 53 normal controls. Multiple domains of memory were assessed, including verbal and nonverbal memory span, verbal and non-verbal paired associate learning, verbal and visual long-term memory, spatial and non-spatial conditional associative learning, recognition memory and memory for temporal order. Consistent with previous studies, substantial deficits in long-term memory were observed, with relative preservation of memory span. Memory for temporal order and recognition memory was intact, although significant deficits were observed on the conditional associative learning tasks. There was no evidence of lateralized memory impairment. In these respects, the pattern of memory impairment in schizophrenia is more similar in nature to that found in patients with memory dysfunction following mesiotemporal lobe lesions, rather than that associated with focal frontal lobe damage. (C) 1999 Elsevier Science B.V. All rights reserved.

The role of working memory capacity in multiple-cue probability learning

Multiple-cue probability learning (MCPL) involves learning to predict a criterion when outcome feedback is provided for multiple cues. A great deal of research suggests that working memory capacity (WMC) is involved in a wide range of tasks that draw on higher level cognitive processes. In three experiments, we examined the role of WMC in MCPL by introducing measures of working memory capacity, as well as other task manipulations. While individual differences in WMC positively predicted performance in some kinds of multiple-cue tasks, performance on other tasks was entirely unrelated to these differences. Performance on tasks that contained negative cues was correlated with working memory capacity, as well as measures of explicit knowledge obtained in the learning process. When the relevant cues predicted positively, however, WMC became irrelevant. The results are discussed in terms of controlled and automatic processes in learning and judgement. © 2011 The Experimental Psychology Society.

Altered long-range alpha-band synchronization during visual short-term memory retention in children born very preterm

Children born very preterm, even when intelligence is broadly normal, often experience selective difficulties in executive function and visual-spatial processing. Development of structural cortical connectivity is known to be altered in this group, and functional magnetic resonance imaging (fMRI) evidence indicates that very preterm children recruit different patterns of functional connectivity between cortical regions during cognition. Synchronization of neural oscillations across brain areas has been proposed as a mechanism for dynamically assigning functional coupling to support perceptual and cognitive processing, but little is known about what role oscillatory synchronization may play in the altered neurocognitive development of very preterm children. To investigate this, we recorded magnetoencephalographic (MEG) activity while 7-8 year old children born very preterm and age-matched full-term controls performed a visual short-term memory task. Very preterm children exhibited reduced long-range synchronization in the alpha-band during visual short-term memory retention, indicating that cortical alpha rhythms may play a critical role in altered patterns functional connectivity expressed by this population during cognitive and perceptual processing. Long-range alpha-band synchronization was also correlated with task performance and visual-perceptual ability within the very preterm group, indicating that altered alpha oscillatory mechanisms mediating transient functional integration between cortical regions may be relevant to selective problems in neurocognitive development in this vulnerable population at school age.

Cortisol, contingency learning, and memory in preterm and full-term infants

Cortisol plays an important role in learning and memory. An inverted-U shaped function has been proposed to account for the positive and negative effects of cortisol on cognitive performance and memory in adults, such that too little or too much impair but moderate amounts facilitate performance. Whether such relationships between cortisol and mental function apply to early infancy, when cortisol secretion, learning, and memory undergo rapid developmental changes, is unknown. We compared relationships between learning/memory and cortisol in preterm and full-term infants and examined whether a greater risk for adrenal insufficiency associated with prematurity produces differential cortisol-memory relationships. Learning in three-month old (corrected for gestational age) preterm and full-term infants was evaluated using a conjugate reinforcement mobile task. Memory was tested by repeating the same task 24h later. Salivary cortisol samples were collected before and 20 min after the presentation of the mobile. We found that preterm infants had lower cortisol levels and smaller cortisol responses than full-term infants. This is consistent with relative adrenal insufficiency reported in the neonatal period. Infants who showed increased cortisol levels from 0 to 20 min on Day 1 had significantly better memory, regardless of prematurity, than infants who showed decreased cortisol levels.

WIQ:Work-intensive query scheduling for in-memory database systems

We propose a novel admission control policy for database queries. Our methodology uses system measurements of CPU utilization and query backlogs to determine interference between queries in execution on the same database server. Query interference may arise due to the concurrent access of hardware and software resources and can affect performance in positive and negative ways. Specifically our admission control considers the mix of jobs in service and prioritizes the query classes consuming CPU resources more efficiently. The policy ignores I/O subsystems and is therefore highly appropriate for in-memory databases. We validate our approach in trace-driven simulation and show performance increases of query slowdowns and throughputs compared to first-come first-served and shortest expected processing time first scheduling. Simulation experiments are parameterized from system traces of a SAP HANA in-memory database installation with TPC-H type workloads. © 2012 IEEE.

A Comparison of Programming Models for Multiprocessors with Explicitly Managed Memory Hierarchies

On multiprocessors with explicitly managed memory hierarchies (EMM), software has the responsibility of moving data in and out of fast local memories. This task can be complex and error-prone even for expert programmers. Before we can allow compilers to handle the complexity for us, we must identify the abstractions that are general enough to allow us to write applications with reasonable effort, yet speci?c enough to exploit the vast on-chip memory bandwidth of EMM multi-processors. To this end, we compare two programming models against hand-tuned codes on the STI Cell, paying attention to programmability and performance. The ?rst programming model, Sequoia, abstracts the memory hierarchy as private address spaces, each corresponding to a parallel task. The second, Cellgen, is a new framework which provides OpenMP-like semantics and the abstraction of a shared address spaces divided into private and shared data. We compare three applications programmed using these models against their hand-optimized counterparts in terms of abstractions, programming complexity, and performance.