Process variation tolerant low power DCT architecture

2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain "good" image quality with Peak Signal to Noise Ratio(PSNR) > 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology.

Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

Multi-Level Wordline Driver for Low Power SRAMs in Nano-Scale CMOS Technology

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.

Increased susceptibility to delayed genetic effects of low dose X-irradiation in DNA repair deficient cells

Purpose: To examine whether the levels of micronuclei induction, as a marker for genomic instability in the progeny of X-irradiated cells, correlates with DNA repair function.

Materials and methods: Two repair deficient cell lines (X-ray repair cross-complementing 1 [XRCC1] deficient cell line [EM9] and X-ray repair cross complementing 5 [XRCC5; Ku80] deficient X-ray sensitive Chinese hamster ovary [CHO] cell line [xrs5]) were used in addition to wild-type CHO cells. These cells were irradiated with low doses of X-rays (up to 1 Gy). Seven days after irradiation, micronuclei formed in binucleated cells were counted. To assess the contribution of the bystander effect micronuclei induction was measured in progeny of non-irradiated cells co-cultured with cells that had been irradiated with 1Gy.

Results: The delayed induction of micronuclei in 1 Gy-irradiated cells was observed in normal CHO and EM9 but not in xrs5. In the clone analysis, progenies of xrs5 under bystander conditions showed significantly higher levels of micronuclei, while CHO and EM9 did not.

Conclusion: Genomic instability induced by X-irradiation is associated with DSB (double-strand break) repair, even at low doses. It is also suggested that bystander signals, which lead to genomic instability, may be enhanced when DSB repair is compromised.

Numerical modelling of low temperature laser produced magnesium plasma

The two-dimensional laser-plasma-interaction hydrodynamic code POLLUX has been used to simulate the ablation of a magnesium target by a 30-ns, 248-nm KrF excimer laser at low laser fluences of ≤10 J cm2. This code, originally written for much higher laser intensities, has been recently extended to include a detailed description of the equation of state in order to treat changes of phase within the target material, and also includes a Thomas Fermi description of the electrons. The simulated temporal and spatial evolution of the plasma plume in the early phase of the expansion (≤100 ns) is compared with experimental interferometric measurements of electron density. The expansion dynamics are in good agreement, although the simulated electron number density is about 2.5 times higher than the experimental values.

Localization Algorithm Performance in Ultra Low Power Active RFID Based Patient Tracking

Indoor personnel localization research has generated a range of potential techniques and algorithms. However, these typically do not account for the influence of the user's body upon the radio channel. In this paper an active RFID based patient tracking system is demonstrated and three localization algorithms are used to estimate the location of a user within a modern office building. It is shown that disregarding body effects reduces the accuracy of the algorithms' location estimates and that body shadowing effects create a systematic position error that estimates the user's location as closer to the RFID reader that the active tag has line of sight to.

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

Dynamics and structure of self-generated magnetics fields on solids following high contrast, high intensity laser irradiation

The dynamics of self-generated magnetic B-fields produced following the interaction of a high contrast, high intensity (I > 10¹⁹W cm^-2) laser beam with thin (3 μm thick) solid (Al or Au) targets is investigated experimentally and numerically. Two main sources drive the growth of B-fields on the target surfaces. B-fields are first driven by laser-generated hot electron currents that relax over ∼10-20 ps. Over longer timescales, the hydrodynamic expansion of the bulk of the target into vacuum also generates B-field induced by non-collinear gradients of density and temperature. The laser irradiation of the target front side strongly localizes the energy deposition at the target front, in contrast to the target rear side, which is heated by fast electrons over a much larger area. This induces an asymmetry in the hydrodynamic expansion between the front and rear target surfaces, and consequently the associated B-fields are found strongly asymmetric. The sole long-lasting (>30 ps) B-fields are the ones growing on the target front surface, where they remain of extremely high strength (∼8-10 MG). These B-fields have been recently put by us in practical use for focusing laser-accelerated protons [B. Albertazzi et al., Rev. Sci. Instrum. 86, 043502 (2015)]; here we analyze in detail their dynamics and structure.

Inexact-aware architecture design for ultra-low power bio-signal analysis

This study introduces an inexact, but ultra-low power, computing architecture devoted to the embedded analysis of bio-signals. The platform operates at extremely low voltage supply levels to minimise energy consumption. In this scenario, the reliability of static RAM (SRAM) memories cannot be guaranteed when using conventional 6-transistor implementations. While error correction codes and dedicated SRAM implementations can ensure correct operations in this near-threshold regime, they incur in significant area and energy overheads, and should therefore be employed judiciously. Herein, the authors propose a novel scheme to design inexact computing architectures that selectively protects memory regions based on their significance, i.e. their impact on the end-to-end quality of service, as dictated by the bio-signal application characteristics. The authors illustrate their scheme on an industrial benchmark application performing the power spectrum analysis of electrocardiograms. Experimental evidence showcases that a significance-based memory protection approach leads to a small degradation in the output quality with respect to an exact implementation, while resulting in substantial energy gains, both in the memory and the processing subsystem.

Heterogeneous error-resilient scheme for spectral analysis in ultra-low power wearable electrocardiogram devices

Wearable devices performing advanced bio-signal analysis algorithms are aimed to foster a revolution in healthcare provision of chronic cardiac diseases. In this context, energy efficiency is of paramount importance, as long-term monitoring must be ensured while relying on a tiny power source. Operating at a scaled supply voltage, just above the threshold voltage, effectively helps in saving substantial energy, but it makes circuits, and especially memories, more prone to errors, threatening the correct execution of algorithms. The use of error detection and correction codes may help to protect the entire memory content, however it incurs in large area and energy overheads which may not be compatible with the tight energy budgets of wearable systems. To cope with this challenge, in this paper we propose to limit the overhead of traditional schemes by selectively detecting and correcting errors only in data highly impacting the end-to-end quality of service of ultra-low power wearable electrocardiogram (ECG) devices. This partition adopts the protection of either significant words or significant bits of each data element, according to the application characteristics (statistical properties of the data in the application buffers), and its impact in determining the output. The proposed heterogeneous error protection scheme in real ECG signals allows substantial energy savings (11% in wearable devices) compared to state-of-the-art approaches, like ECC, in which the whole memory is protected against errors. At the same time, it also results in negligible output quality degradation in the evaluated power spectrum analysis application of ECG signals.

Efficient low-power design and implementation of IQ-imbalance compensator using early termination

In this paper, we propose a low-complexity architecture for the implementation of adaptive IQ-imbalance compensation in quadrature zero-IF receivers. Our blind IQ-compensation scheme jointly compensates for IQ phase and gain errors without the need for test/pilot tones. The proposed architecture employs early-termination of the iteration process; this enables the powering-down of the parts of the adaptive algorithm thereby saving power. The complexity, in terms of power-down efficiency is evaluated and shows a reduction by 37-50 % for 32-PSK and 37-58 % for 64-QAM modulated signals.