Monodisperse raspberry-like gold submicrometer spheres: Large-scale synthesis and interface assembling for colloid sphere array

We first suggested a one-pot method to synthesize monodisperse raspberry-like submicrometer gold spheres (MRSGS) with high yield. The resulting gold spheres were characterized by scanning electron microscopy, transmission electron microscopy, energy-dispersed X-ray spectroscopy, X-ray photoelectron spectroscopy, X-ray diffraction, and electrochemical technology. It was found that the rough structure provided by raspberry-like gold spheres led to a tremendous electrochemical active area, which was very important because these novel hierarchical gold spheres will probably find important applications in biosensors, electrocatalysis, and others.

Rectangular Silver Nanorods: Controlled Preparation, Liquid-Liquid Interface Assembly, and Application in Surface-Enhanced Raman Scattering

In this paper, we for the first time report a polyol method for large-scale synthesis of rectangular silver nanorods in the presence of directing agent and seeds. This method has some clear advantages including simplicity, high quality, and ease of scaleup. Silver nanowires or silver nanorods with a submicrometer diameter could also be facilely prepared when the reaction parameters are slightly changed. Furthermore, a liquid-liquid assembly strategy has been employed to construct uniform rectangular silver nanorod arrays on a solid substrate which could be used as surface-enhanced Raman scattering (SERS) substrates with high SERS activity, stability, and reproducibility. It is found that the SERS spectra obtained from the probe molecules with the different concentrations show different SERS intensifies. As the concentration of 4-aminothiophenol (4-ATP) or rhodamine 6G (R6G) increases, the SERS intensities progressively increase. The enhancement factor for 4-ATP and R6G should be as large as 5.06 x 10(4) or much larger than the value of 5.06 x 10(8), respectively.

Spontaneous formation of two-dimensional gold networks at the air-water interface and their application in surface-enhanced Raman scattering (SERS)

Two-dimensional (2-D) gold networks were spontaneously formed at the air-water interface after HAuCl4 reacted with fructose at 90 degrees C in a sealed vessel, in a reaction in which fructose acted as both a reducing and a protecting agent. Through fine-tuning of the molar ratio of HAuCl4 to fructose, the thus-formed 2-D gold networks can be changed from a coalesced pattern to an interconnected pattern. In the coalesced pattern, some well-defined single-crystalline gold plates at the micrometer-scale could be seen, while in the interconnected pattern, many sub-micrometer particles and some irregular gold plates instead of well-defined gold plates appeared. It is also found that the 2-D gold networks in the form of an interconnected pattern can be used as substrates for surface-enhanced Raman scattering (SERS) because of the strong localized electromagnetic field produced by the gaps between the neighboring particles in the 2-D gold networks.

Reactive reinforcement of the interface of high performance polymer blends by PMR-POI

The effect of PMR-polyimide(POI) as the interfacial agent on the interface characteristics, morphology features and crystallization of poly (ether sulfone) /poly (phenylene sulfide) (PES/PPS) and poly(ether ether ketone)/poly (ether sulfone) (PEEK/PES) partly miscible blends were investigated by means of the scanning electron microscopy, WAXD and XPS surface analysis. It is found that the interfacial adhesion was enhanced remarkably, the size of the dispersed phase particles was reduced significantly and the miscibility was improved by the addition of POI. During melt blending cross-link and/or grafting reaction of POI with PES, PEEK and PPS homopolymers was detected, however the reaction activity of POI with PPS was much higher than that of PES and PEEK. It was also found that POI was an effective nucleation agent of the crystallization of PPS.

BitBox!: A case study interface for teaching real-time adaptive music composition for video games

Real-time adaptive music is now well-established as a popular medium, largely through its use in video game soundtracks. Commercial packages, such as fmod, make freely available the underlying technical methods for use in educational contexts, making adaptive music technologies accessible to students. Writing adaptive music, however, presents a significant learning challenge, not least because it requires a different mode of thought, and tutor and learner may have few mutual points of connection in discovering and understanding the musical drivers, relationships and structures in these works. This article discusses the creation of ‘BitBox!’, a gestural music interface designed to deconstruct and explain the component elements of adaptive composition through interactive play. The interface was displayed at the Dare Protoplay games exposition in Dundee in August 2014. The initial proof-of- concept study proved successful, suggesting possible refinements in design and a broader range of applications.

SymbolDesign: A User-centered Method to Design Pen-based Interfaces and Extend the Functionality of Pointer Input Devices

A method called "SymbolDesign" is proposed that can be used to design user-centered interfaces for pen-based input devices. It can also extend the functionality of pointer input devices such as the traditional computer mouse or the Camera Mouse, a camera-based computer interface. Users can create their own interfaces by choosing single-stroke movement patterns that are convenient to draw with the selected input device and by mapping them to a desired set of commands. A pattern could be the trace of a moving finger detected with the Camera Mouse or a symbol drawn with an optical pen. The core of the SymbolDesign system is a dynamically created classifier, in the current implementation an artificial neural network. The architecture of the neural network automatically adjusts according to the complexity of the classification task. In experiments, subjects used the SymbolDesign method to design and test the interfaces they created, for example, to browse the web. The experiments demonstrated good recognition accuracy and responsiveness of the user interfaces. The method provided an easily-designed and easily-used computer input mechanism for people without physical limitations, and, with some modifications, has the potential to become a computer access tool for people with severe paralysis.

Extending snBench to Support a Graphical Programming Interface for a Sensor Network Tasking Language (STEP)

The purpose of this project is the creation of a graphical "programming" interface for a sensor network tasking language called STEP. The graphical interface allows the user to specify a program execution graphically from an extensible pallet of functionalities and save the results as a properly formatted STEP file. Moreover, the software is able to load a file in STEP format and convert it into the corresponding graphical representation. During both phases a type-checker is running on the background to ensure that both the graphical representation and the STEP file are syntactically correct. This project has been motivated by the Sensorium project at Boston University. In this technical report we present the basic features of the software, the process that has been followed during the design and implementation. Finally, we describe the approach used to test and validate our software.

Wireless sensor node design for heterogeneous networks

Two complementary wireless sensor nodes for building two-tiered heterogeneous networks are presented. A larger node with a 25 mm by 25 mm size acts as the backbone of the network, and can handle complex data processing. A smaller, cheaper node with a 10 mm by 10 mm size can perform simpler sensor-interfacing tasks. The 25mm node is based on previous work that has been done in the Tyndall National Institute that created a modular wireless sensor node. In this work, a new 25mm module is developed operating in the 433/868 MHz frequency bands, with a range of 3.8 km. The 10mm node is highly miniaturised, while retaining a high level of modularity. It has been designed to support very energy efficient operation for applications with low duty cycles, with a sleep current of 3.3 μA. Both nodes use commercially available components and have low manufacturing costs to allow the construction of large networks. In addition, interface boards for communicating with nodes have been developed for both the 25mm and 10mm nodes. These interface boards provide a USB connection, and support recharging of a Li-ion battery from the USB power supply. This paper discusses the design goals, the design methods, and the resulting implementation.

Hardware design of cryptographic accelerators

With the rapid growth of the Internet and digital communications, the volume of sensitive electronic transactions being transferred and stored over and on insecure media has increased dramatically in recent years. The growing demand for cryptographic systems to secure this data, across a multitude of platforms, ranging from large servers to small mobile devices and smart cards, has necessitated research into low cost, flexible and secure solutions. As constraints on architectures such as area, speed and power become key factors in choosing a cryptosystem, methods for speeding up the development and evaluation process are necessary. This thesis investigates flexible hardware architectures for the main components of a cryptographic system. Dedicated hardware accelerators can provide significant performance improvements when compared to implementations on general purpose processors. Each of the designs proposed are analysed in terms of speed, area, power, energy and efficiency. Field Programmable Gate Arrays (FPGAs) are chosen as the development platform due to their fast development time and reconfigurable nature. Firstly, a reconfigurable architecture for performing elliptic curve point scalar multiplication on an FPGA is presented. Elliptic curve cryptography is one such method to secure data, offering similar security levels to traditional systems, such as RSA, but with smaller key sizes, translating into lower memory and bandwidth requirements. The architecture is implemented using different underlying algorithms and coordinates for dedicated Double-and-Add algorithms, twisted Edwards algorithms and SPA secure algorithms, and its power consumption and energy on an FPGA measured. Hardware implementation results for these new algorithms are compared against their software counterparts and the best choices for minimum area-time and area-energy circuits are then identified and examined for larger key and field sizes. Secondly, implementation methods for another component of a cryptographic system, namely hash functions, developed in the recently concluded SHA-3 hash competition are presented. Various designs from the three rounds of the NIST run competition are implemented on FPGA along with an interface to allow fair comparison of the different hash functions when operating in a standardised and constrained environment. Different methods of implementation for the designs and their subsequent performance is examined in terms of throughput, area and energy costs using various constraint metrics. Comparing many different implementation methods and algorithms is nontrivial. Another aim of this thesis is the development of generic interfaces used both to reduce implementation and test time and also to enable fair baseline comparisons of different algorithms when operating in a standardised and constrained environment. Finally, a hardware-software co-design cryptographic architecture is presented. This architecture is capable of supporting multiple types of cryptographic algorithms and is described through an application for performing public key cryptography, namely the Elliptic Curve Digital Signature Algorithm (ECDSA). This architecture makes use of the elliptic curve architecture and the hash functions described previously. These components, along with a random number generator, provide hardware acceleration for a Microblaze based cryptographic system. The trade-off in terms of performance for flexibility is discussed using dedicated software, and hardware-software co-design implementations of the elliptic curve point scalar multiplication block. Results are then presented in terms of the overall cryptographic system.

Plasmonic Nanoparticles and Nanowires: Design, Fabrication and Application in Sensing.

This study involves two aspects of our investigations of plasmonics-active systems: (i) theoretical and simulation studies and (ii) experimental fabrication of plasmonics-active nanostructures. Two types of nanostructures are selected as the model systems for their unique plasmonics properties: (1) nanoparticles and (2) nanowires on substrate. Special focus is devoted to regions where the electromagnetic field is strongly concentrated by the metallic nanostructures or between nanostructures. The theoretical investigations deal with dimers of nanoparticles and nanoshells using a semi-analytical method based on a multipole expansion (ME) and the finite-element method (FEM) in order to determine the electromagnetic enhancement, especially at the interface areas of two adjacent nanoparticles. The experimental study involves the design of plasmonics-active nanowire arrays on substrates that can provide efficient electromagnetic enhancement in regions around and between the nanostructures. Fabrication of these nanowire structures over large chip-scale areas (from a few millimeters to a few centimeters) as well as FDTD simulations to estimate the EM fields between the nanowires are described. The application of these nanowire chips using surface-enhanced Raman scattering (SERS) for detection of chemicals and labeled DNA molecules is described to illustrate the potential of the plasmonics chips for sensing.

Multiphysics modelling for electronics design

The future of many companies will depend to a large extent on their ability to initiate techniques that bring schedules, performance, tests, support, production, life-cycle-costs, reliability prediction and quality control into the earliest stages of the product creation process. Important questions for an engineer who is responsible for the quality of electronic parts such as printed circuit boards (PCBs) during design, production, assembly and after-sales support are: What is the impact of temperature? What is the impact of this temperature on the stress produced in the components? What is the electromagnetic compatibility (EMC) associated with such a design? At present, thermal, stress and EMC calculations are undertaken using different software tools that each require model build and meshing. This leads to a large investment in time, and hence cost, to undertake each of these simulations. This paper discusses the progression towards a fully integrated software environment, based on a common data model and user interface, having the capability to predict temperature, stress and EMC fields in a coupled manner. Such a modelling environment used early within the design stage of an electronic product will provide engineers with fast solutions to questions regarding thermal, stress and EMC issues. The paper concentrates on recent developments in creating such an integrated modeling environment with preliminary results from the analyses conducted. Further research into the thermal and stress related aspects of the paper is being conducted under a nationally funded project, while their application in reliability prediction will be addressed in a new European project called PROFIT.

Towards the design of a portal framework for web services integration

Web services based systems have recently found their way into many applications such as e-commerce, corporate integration and e-learning. Construction of new services or introducing new functions to existing services requires composition of web services. Current approaches to service composition often require major programming effort; this is time consuming and requires considerable developer expertise. In this paper, we explore the real and rich scenarios found in e-learning where education services are offered through the Internet by networked universities to potentially millions in the world. These services are derived from existing/emerging business operation processes and commonly offered through a web interface, combined with other services such as email and ftp services, to support partial/full business processes. We identify the requirements for a generic portal framework for easy integration of existing expertise and services of individual institutions (enterprises). We examine the existing technologies and standards, and point out the gaps to be filled in designing the architecture of the framework

A design pattern for integration of business process management systems

A cross-domain workflow application may be constructed using a standard reference model such as the one by the Workflow Management Coalition (WfMC) [7] but the requirements for this type of application are inherently different from one organization to another. The existing models and systems built around them meet some but not all the requirements from all the organizations involved in a collaborative process. Furthermore the requirements change over time. This makes the applications difficult to develop and distribute. Service Oriented Architecture (SOA) based approaches such as the BPET (Business Process Execution Language) intend to provide a solution but fail to address the problems sufficiently, especially in the situations where the expectations and level of skills of the users (e.g. the participants of the processes) in different organisations are likely to be different. In this paper, we discuss a design pattern that provides a novel approach towards a solution. In the solution, business users can design the applications at a high level of abstraction: the use cases and user interactions; the designs are documented and used, together with the data and events captured later that represents the user interactions with the systems, to feed an intermediate component local to the users -the IFM (InterFace Mapper) -which bridges the gaps between the users and the systems. We discuss the main issues faced in the design and prototyping. The approach alleviates the need for re-programming with the APIs to any back-end service thus easing the development and distribution of the applications

Design of parallel algorithms for fractal video compression

The intrinsic independent features of the optimal codebook cubes searching process in fractal video compression systems are examined and exploited. The design of a suitable parallel algorithm reflecting the concept is presented. The Message Passing Interface (MPI) is chosen to be the communication tool for the implementation of the parallel algorithm on distributed memory parallel computers. Experimental results show that the parallel algorithm is able to reduce the compression time and achieve a high speed-up without changing the compression ratio and the quality of the decompressed image. A scalability test was also performed, and the results show that this parallel algorithm is scalable.

Investigating the representation of merging behavior at the floor–stair interface in computer simulations of multi-floor building evacuations

In this article, the representation of the merging process at the floor— stair interface is examined within a comprehensive evacuation model and trends found in experimental data are compared with model predictions. The analysis suggests that the representation of floor—stair merging within the comprehensive model appears to be consistent with trends observed within several published experiments of the merging process. In particular: (a) The floor flow rate onto the stairs decreases as the stair population density increases. (b) For a given stair population density, the floor population's flow rate onto the stairs can be maximized by connecting the floor to the landing adjacent to the incoming stair. (c) In situations where the floor is connected adjacent to the incoming stair, the merging process appears to be biased in favor of the floor population. It is further conjectured that when the floor is connected opposite the incoming stair, the merging process between the stair and floor streams is almost in balance for high stair population densities, with a slight bias in favor of the floor stream at low population densities. A key practical finding of this analysis is that the speed at which a floor can be emptied onto a stair can be enhanced simply by connecting the floor to the landing at a location adjacent to the incoming stair rather than opposite the stair. Configuring the stair in this way, while reducing the floor emptying time, results in a corresponding decrease in the descent flow rate of those already on the stairs. While this is expected to have a negligible impact on the overall time to evacuate the building, the evacuation time for those higher up in the building is extended while those on the lower flows is reduced. It is thus suggested that in high-rise buildings, floors should be connected to the landing on the opposite side to the incoming stair. Information of this type will allow engineers to better design stair—floor interfaces to meet specific design objectives.