Open Technologies for prototyping the Internet of Things

The worldwide "hyper-connection" of any object around us is the challenge that promises to cover the paradigm of the Internet of Things. If the Internet has colonized the daily life of more than 2000 million1 people around the globe, the Internet of Things faces of connecting more than 100000 million2 "things" by 2020. The underlying Internet of Things��� technologies are the cornerstone that promises to solve interrelated global problems such as exponential population growth, energy management in cities, and environmental sustainability in the average and long term. On the one hand, this Project has the goal of knowledge acquisition about prototyping technologies available in the market for the Internet of Things. On the other hand, the Project focuses on the development of a system for devices management within a Wireless Sensor and Actuator Network to offer some services accessible from the Internet. To accomplish the objectives, the Project will begin with a detailed analysis of various ���open source��� hardware platforms to encourage creative development of applications, and automatically extract information from the environment around them for transmission to external systems. In addition, web platforms that enable mass storage with the philosophy of the Internet of Things will be studied. The project will culminate in the proposal and specification of a service-oriented software architecture for embedded systems that allows communication between devices on the network, and the data transmission to external systems. Furthermore, it abstracts the complexities of hardware to application developers. RESUMEN. La ���hiper-conexi��n��� a nivel mundial de cualquier objeto que nos rodea es el desaf��o al que promete dar cobertura el paradigma de la Internet de las Cosas. Si la Internet ha colonizado el d��a a d��a de m��s de 2000 millones1 de personas en todo el planeta, la Internet de las Cosas plantea el reto de conectar a m��s de 100000 millones2 de ���cosas��� para el a��o 2020. Las tecnolog��as subyacentes de la Internet de las Cosas son la piedra angular que prometen dar soluci��n a problemas globales interrelacionados como el crecimiento exponencial de la poblaci��n, la gesti��n de la energ��a en las ciudades o la sostenibilidad del medioambiente a largo plazo. Este Proyecto Fin de Carrera tiene como principales objetivos por un lado, la adquisici��n de conocimientos acerca de las tecnolog��as para prototipos disponibles en el mercado para la Internet de las Cosas, y por otro lado el desarrollo de un sistema para la gesti��n de dispositivos de una red inal��mbrica de sensores que ofrezcan unos servicios accesibles desde la Internet. Con el fin de abordar los objetivos marcados, el proyecto comenzar�� con un an��lisis detallado de varias plataformas hardware de tipo ���open source��� que estimulen el desarrollo creativo de aplicaciones y que permitan extraer de forma autom��tica informaci��n del medio que les rodea para transmitirlo a sistemas externos para su posterior procesamiento. Por otro lado, se estudiar��n plataformas web identificadas con la filosof��a de la Internet de las Cosas que permitan el almacenamiento masivo de datos que diferentes plataformas hardware transfieren a trav��s de la Internet. El Proyecto culminar�� con la propuesta y la especificaci��n una arquitectura software orientada a servicios para sistemas empotrados que permita la comunicaci��n entre los dispositivos de la red y la transmisi��n de datos a sistemas externos, as�� como facilitar el desarrollo de aplicaciones a los programadores mediante la abstracci��n de la complejidad del hardware.

Middleware architectures for the Smart Grid : survey and challenges in the foreseeable future

The traditional power grid is just a one-way supplier that gets no feedback data about the energy delivered, what tariffs could be the most suitable ones for customers, the shifting daily needs of electricity in a facility, etc. Therefore, it is only natural that efforts are being invested in improving power grid behavior and turning it into a Smart Grid. However, to this end, several components have to be either upgraded or created from scratch. Among the new components required, middleware appears as a critical one, for it will abstract all the diversity of the used devices for power transmission (smart meters, embedded systems, etc.) and will provide the application layer with a homogeneous interface involving power production and consumption management data that were not able to be provided before. Additionally, middleware is expected to guarantee that updates to the current metering infrastructure (changes in service or hardware availability) or any added legacy measuring appliance will get acknowledged for any future request. Finally, semantic features are of major importance to tackle scalability and interoperability issues. A survey on the most prominent middleware architectures for Smart Grids is presented in this paper, along with an evaluation of their features and their strong points and weaknesses.

Languages for safety-certification related propertis

The Safety Certification of Software-Intensive Systems with Reusable Components project, in short SafeCer (www.safecer.eu),is targeting increased efficiency and reduced time-to-market by composable safety certification of safety- relevant embedded systems. The industrial domains targeted are within automotive and construction equipment, avionics, and rail. Some of the companies involved are: Volvo Tech- nology, Thales, TTTech, and Intecs among others. SafeCer includes more than 30 partners in six different countries and has a budget of e25.7 millions. A primary objective is to provide support for system safety arguments based on arguments and properties of system components as well as to provide support for generation of corresponding evidence in a similar compositional way. By providing support for efficient reuse of certification and stronger links between certification and development, compo- nent reuse will be facilitated, and by providing support for reuse across domains the amount of components available for reuse will increase dramatically. The resulting efficiency and reduced time to market will, together with increased quality and reduced risk, increase competitiveness and pave the way for a cross-domain market for software components qualified for certification.

Adapting mode switches into the hierarchical scheduling

Mode switches are used to partition the system���s behavior into different modes to reduce the complexity of large embedded systems. Such systems operate in multiple modes in which each one corresponds to a specific application scenario; these are called Multi-Mode Systems (MMS). A different piece of software is normally executed for each mode. At any given time, the system can be in one of the predefined modes and then be switched to another as a result of a certain condition. A mode switch mechanism (or mode change protocol) is used to shift the system from one mode to another at run-time. In this thesis we have used a hierarchical scheduling framework to implement a multi-mode system called Multi-Mode Hierarchical Scheduling Framework (MMHSF). A two-level Hierarchical Scheduling Framework (HSF) has already been implemented in an open source real-time operating system, FreeRTOS, to support temporal isolation among real-time components. The main contribution of this thesis is the extension of the HSF featuring a multimode feature with an emphasis on making minimal changes in the underlying operating system (FreeRTOS) and its HSF implementation. Our implementation uses fixed-priority preemptive scheduling at both local and global scheduling levels and idling periodic servers. It also now supports different modes of the system which can be switched at run-time. Each subsystem and task exhibit different timing attributes according to mode, and upon a Mode Change Request (MCR) the task-set and timing interfaces of the entire system (including subsystems and tasks) undergo a change. A Mode Change Protocol specifies precisely how the system-mode will be changed. However, an application may not only need to change a mode but also a different mode change protocol semantic. For example, the mode change from normal to shutdown can allow all the tasks to be completed before the mode itself is changed, while changing a mode from normal to emergency may require aborting all tasks instantly. In our work, both the system mode and the mode change protocol can be changed at run-time. We have implemented three different mode change protocols to switch from one mode to another: the Suspend/resume protocol, the Abort protocol, and the Complete protocol. These protocols increase the flexibility of the system, allowing users to select the way they want to switch to a new mode. The implementation of MMHSF is tested and evaluated on an AVR-based 32 bit board EVK1100 with an AVR32UC3A0512 micro-controller. We have tested the behavior of each system mode and for each mode change protocol. We also provide the results for the performance measures of all mode change protocols in the thesis. RESUMEN Los conmutadores de modo son usados para particionar el comportamiento del sistema en diferentes modos, reduciendo as�� la complejidad de grandes sistemas empotrados. Estos sistemas tienen multiples modos de operaci��n, cada uno de ellos correspondiente a distintos escenarios y para distintas aplicaciones; son llamados Sistemas Multimodales (o en ingl��s ���Multi-Mode Systems��� o MMS). Normalmente cada modo ejecuta una parte de c��digo distinto. En un momento dado el sistema, que est�� en un modo concreto, puede ser cambiado a otro modo distinto como resultado de alguna condicion impuesta previamente. Los mecanismos de cambio de modo (o protocolos de cambio de modo) son usados para mover el sistema de un modo a otro durante el tiempo de ejecuci��n. En este trabajo se ha usado un modelo de sistema operativo para implementar un sistema multimodo llamado MMHSF, siglas en ingl��s correspondientes a (Multi-Mode Hierarchical Scheduling Framework). Este sistema est�� basado en el HSF (Hierarchical Scheduling Framework), un modelo de sistema operativo con jerarqu��a de dos niveles, implementado en un sistema operativo en tiempo real de libre distribuci��n llamado FreeRTOS, capaz de permitir el aislamiento temporal entre componentes. La principal contribuci��n de este trabajo es la ampliaci��n del HSF convirtiendolo en un sistema multimodo realizando los cambios m��nimos necesarios sobre el sistema operativo FreeRTOS y la implementaci��n ya existente del HSF. Esta implementaci��n usa un sistema de planificaci��n de prioridad fija para ambos niveles de jerarqu��a, ocupando el tiempo entre tareas con un ���modo reposo���. Adem��s el sistema es capaz de cambiar de un modo a otro en tiempo de ejecuci��n. Cada subsistema y tarea son capaces de tener distintos atributos de tiempo (prioridad, periodo y tiempo de ejecuci��n) en funci��n del modo. Bajo una demanda de cambio de modo (Mode Change Request MCR) se puede variar el set de tareas en ejecuci��n, as�� como los atributos de los servidores y las tareas. Un protocolo de cambio de modo espeficica precisamente c��mo ser�� cambiado el sistema de un modo a otro. Sin embargo una aplicaci��n puede requerir no solo un cambio de modo, sino que lo haga de una forma especifica. Por ejemplo, el cambio de modo de ���normal��� a ���apagado��� puede permitir a las tareas en ejecuci��n ser finalizadas antes de que se complete la transici��n, pero sin embargo el cambio de ���normal��� a ���emergencia��� puede requerir abortar todas las tareas instantaneamente. En este trabajo ambas caracter��sticas, tanto el modo como el protocolo de cambio, pueden ser cambiadas en tiempo de ejecuci��n, pero deben ser previamente definidas por el desarrollador. Han sido definidos tres protocolos de cambios: el protocolo ���suspender/continuar���, protocolo ���abortar��� y el protocolo ���completar���. Estos protocolos incrementan la flexibilidad del sistema, permitiendo al usuario seleccionar de que forma quieren cambiar hacia el nuevo modo. La implementaci��n del MMHSF ha sido testada y evaluada en una placa AVR EVK1100, con un micro-controlador AVR32UC3A0. Se ha comprobado el comportamiento de los distintos modos para los distintos protocolos, definidos previamente. Como resultado se proporcionan las medidades de rendimiento de los distintos protocolos de cambio de modo.

T��cnicas de dise��o de pruebas en sistemas embebidos

El software es, cada vez m��s, una parte muy importante de cualquier circuito electr��nico moderno, por ejemplo, un circuito realizado con alg��n tipo de microprocesador debe incorporar un programa de control por peque��o que sea. Al utilizarse programas inform��ticos en los circuitos electr��nicos modernos, es muy aconsejable, por no decir imprescindible, realizar una serie de pruebas de calidad del dise��o realizado. Estas pruebas son cada vez m��s complicadas de realizar debido al gran tama��o del software empleado en los sistemas actuales, por este motivo, es necesario estructurar una serie de pruebas con el fin de realizar un sistema de calidad, y en algunos casos, un sistema que no presente ning��n peligro para el ser humano o el medio ambiente. Esta propuesta consta de la explicaci��n de las t��cnicas de dise��o de pruebas que existen actualmente (por lo menos las m��s b��sicas ya que es un tema muy extenso) para realizar el control de calidad del software que puede contener un sistema embebido. Adem��s, muchos circuitos electr��nicos, debido a su control o exigencia hardware, es imprescindible que sean manipulados por alg��n programa que requiera m��s que un simple microprocesador, me refiero a que se deban controlar por medio de un peque��o programa manipulado por un sistema operativo, ya sea Linux, AIX, Unix, Windows, etc., en este caso el control de calidad se deber��a llevar a cabo con otras t��cnicas de dise��o. Tambi��n se puede dar el caso que el circuito electr��nico a controlar se deba hacer por medio de una p��gina web. El objetivo es realizar un estudio de las actuales t��cnicas de dise��o de pruebas que est��n orientadas al desarrollo de sistemas embebidos. ABSTRACT. Software is increasingly a very important part of any modern electronic circuit, for example, a circuit made with some type of microprocessor must incorporate a control program no matter the small it is. When computer programs are used in modern electronic circuits, it is quite advisable if not indispensable to perform a series of quality tests of the design. These tests are becoming more and more difficult to be performed due to the large size of the software used in current systems, which is why it is necessary to structure a series of tests in order to perform a quality system, and in some cases, a system with no danger to humans or to the environment. This proposal consists of an explanation of the techniques used in the tests (at least the most basic ones since it is a very large topic) for quality control of software which may contain an embedded system. In addition, a lot of electronic circuits, due to its control or required hardware, it is essential to be manipulated by a program that requires more than a simple microprocessor, I mean that they must be controlled by means of a small program handled by an operating system, being Linux, AIX, Unix, Windows, etc., in this case the quality control should be carried out with other design techniques. The objective is to study the current test design techniques that are geared to the development of embedded systems. It can also occur that the electronic circuit should be controlled by means of a web page.

Desarrollo de un sistema autom��tico de medida para el control del consumo en sistemas empotrados

El Grupo de Dise��o Electr��nico y Microelectr��nico de la Universidad Polit��cnica de Madrid -GDEM- se dedica, entre otras cosas, al estudio y mejora del consumo en sistemas empotrados. Es en este lugar y sobre este tema donde el proyecto a exponer ha tomado forma y desarrollo. Seg��n un art��culo de la revista online Revista de Electr��nica Embebida, un sistema empotrado o embebido es aquel ���sistema controlado por un microprocesador y que gracias a la programaci��n que incorpora o que se le debe incorporar, realiza una funci��n espec��fica para la que ha sido dise��ado, integrando en su interior la mayor��a de los elementos necesarios para realizar dicho funci��n���. El porqu�� de estudiar sobre este tema responde a que, cada vez, hay mayor presencia de sistemas empotrados en nuestra vida cotidiana. Esto es debido a que se est�� tendiendo a dotar de ���inteligencia��� a todo lo que puedan hacer nuestra vida un poco m��s f��cil. Nos podemos encontrar dichos sistemas en f��bricas, oficinas de atenci��n a los ciudadanos, sistemas de seguridad de hogar, relojes, m��viles, lavadoras, hornos, aspiradores y un largo etc��tera en cualquier aparato que nos podamos imaginar. A pesar de sus grandes ventajas, a��n hay grandes inconvenientes. El mayor problema que supone a d��a de hoy es la autonom��a del mismo sistema, ya que hablamos de aparatos que muchas veces est��n alimentados por bater��as -para ayudar a su portabilidad���. Por esto, se est�� intentando dotar a dichos sistemas de una capacidad de ahorro de energ��a y toma de decisiones que podr��an ayudar a duplicar la autonom��a de dicha bater��a. Un ejemplo claro son los Smartphones de hoy en d��a, unos aparatos casi indispensables que pueden tener una autonom��a de un d��a. Esto es poco pr��ctico para el usuario en caso de viajes, trabajo u otras situaciones en las que se le d�� mucho uso y no pueda tener acceso a una red el��ctrica. Es por esto que surge la necesidad de investigar, sin necesidad de mejorar el hardware del sistema, una manera de mejorar esta situaci��n. Este proyecto trabajar�� en esa l��nea creando un sistema autom��tico de medida el cual generar�� las corrientes que servir��n como entrada para verificar el sistema de adquisici��n que junto con la tarjeta Beagle Board permitir�� la toma de decisiones en relaci��n con el consumo de energ��a. Para realizar este sistema, nos ayudaremos de diferentes herramientas que podremos encontrar en el laboratorio del GDEM, como la fuente de alimentaci��n Agilent y la Beagle Board ���como principales herramientas de trabajo- . El objetivo principal ser�� la simulaci��n de unas se��ales que, despu��s de pasar un proceso de conversi��n y tratado, har��n la funci��n de representaci��n del consumo de cada una de las partes que pueden formar un sistema empotrado gen��rico. Por lo tanto, podemos decir que el sistema har�� la funcionalidad de un banco de pruebas que ayudar�� a simular dicho consumo para que el microprocesador del sistema pueda llegar a tomar alguna decisi��n. ABSTRACT. The Electronic and Microelectronic Design Group of Universidad Polit��cnica de Madrid -GDEM- is in charge, between other issues, of improving the embedded system���s consumption. It is in this place and about this subject where the exposed project has taken shape and development. According to an article from de online magazine Revista de Electronica Embebida, an embedded system is ���the one controlled by a microprocessor and, thanks to the programing that it includes, it carries out a specific function what it has been designed for, being integrated in it the most necessary elements for realizing the already said function���. The because of studying this subject, answers that each time there is more presence of the embedded system in our daily life. This is due to the tendency of providing ���intelligence��� to all what can make our lives easier. We can find this kind of systems in factories, offices, security systems, watchers, mobile phones, washing machines, ovens, hoovers and, definitely, in all kind of machines what we can think of. Despite its large vantages, there are still some inconveniences. Nowadays, the most important problem is the autonomy of the system itself when machines that have to be supplied by batteries ���making easier the portability-. Therefore, this project is going after a save capacity of energy for the system as well as being able to take decisions in order to duplicate batteries��� autonomy. Smartphones are a clear example. They are a very successful product but the autonomy is just one day. This is not practical for users, at all, if they have to travel, to work or to do any activity that involves a huge use of the phone without a socket nearby. That is why the need of investigating a way to improve this situation. This project is working on this line, creating an automatic system that will generate the currents for verifying the acquisition system that, with the beagle board, will help taking decisions regarding the energy���s consumption. To carry out this system, we need different tools that we can find in the laboratory of the group previously mentioned, like power supply Agilent and the Beagle Board ��� as main working tools ���. The main goal is the simulation of some signals that, after a conversion process, will represent de consumption of each of the parts in the embedded generic system. Therefore, the system will be a testing ground that simulate the consumption, once sent to the processor, to be processed and so the microprocessor system might take some decision.

Hammer: an Android based application for end-user industrial robot programming

This paper presents a novel tablet based end-user interface for industrial robot programming (called Hammer). This application makes easier to program tasks for industrial robots like polishing, milling or grinding. It is based on the Scratch programming language, but specifically design and created for Android OS. It is a visual programming concept that allows non-skilled programmer operators to create programs. The application also allows to monitor the tasks while it is being executed by overlapping real time information through augmented reality. The application includes a teach pendant screen that can be customized according to the operator needs at every moment.

Mixed-criticality design of a satellite software system

The continuous increment of processors computational power and the requirements on additional functionality and services are motivating a change in the way embedded systems are built. Components with different criticality level are allocated in the same processor, which give rise to mixed-criticality systems. The use of partitioned systems is a way of preventing undesirable interferences between components with different criticality level. An hypervisor provides these partitions or virtual machines, ensuring spatial, temporal and fault isolation between them. The purpose of this paper is to illustrate the development of a mixed-critical system. The attitude control subsystem is used for showing the different steps, which are supported by a toolset developed in the context of the MultiPARTES research project.

A Dynamically Adaptable Image Processing Application Trading Off Between High Performance, Consumption and Dependability in Real Time

As embedded systems evolve, problems inherent to technology become important limitations. In less than ten years, chips will exceed the maximum allowed power consumption affecting performance, since, even though the resources available per chip are increasing, frequency of operation has stalled. Besides, as the level of integration is increased, it is difficult to keep defect density under control, so new fault tolerant techniques are required. In this demo work, a new dynamically adaptable virtual architecture (ARTICo3) to allow dynamic and context-aware use of resources is implemented in a high performance Wireless Sensor node (HiReCookie) to perform an image processing application.

Integraci��n de RVC-HEVC y OpenHEVC sobre la plataforma MultiDSP C6678

Este proyecto se basa en la integraci��n de funciones optimizadas de OpenHEVC en el c��dec Reconfigurable Video Coding (RVC) - High Efficiency Video Coding (HEVC). RVC es un framework capaz de generar autom��ticamente el c��digo que implementa cualquier est��ndar de video mediante el uso de librer��as. Estas librer��as contienen la definici��n de bloques funcionales de los que se componen los distintos est��ndares de video a implementar. Sin embargo, como desventaja a la facilidad de creaci��n de est��ndares utilizando este framework, las librer��as que utiliza no se encuentran optimizadas. Por ello se pretende que el c��dec RVC-HEVC sea capaz de realizar llamadas a funciones optimizadas, que para el estudio ��stas se encontrar��n en la librer��a OpenHEVC. Por otro lado, estos codificadores de video se pueden encontrar implementados tanto en PCs como en sistemas embebidos. Los Digital Signal Processors (DSPs) son unas plataformas especializadas en el procesamiento digital, teniendo una alta velocidad en el c��mputo de operaciones matem��ticas. Por ello, para este proyecto se integrar�� RVC-HEVC con las llamadas a OpenHEVC en una plataforma DSP como la TMS320C6678. Una vez completa la integraci��n se efectuan medidas de eficiencia para ver c��mo las llamadas a funciones optimizadas mejoran la velocidad en la decodificaci��n de im��genes. ABSTRACT. This project is based in the integration of optimized functions from OpenHEVC in the RVC-HEVC (Reconfigurable Video Coding- High Efficiency Video Coding) codec. RVC is a framework capable of generating automatically any type of video standard with the use of libraries. Inside these libraries there are the definitions of the functional blocks which make up the different standards, in which for the case of study will be the HEVC standard. Nevertheless, as a downside for the simplicity in producing standards with the RVC tool, these libraries are not optimized. Thus, one of the goals for the project will be to make the RVC-HEVC call optimized functions, in which in this case they will be inside the OpenHEVC library. On the other hand, these video encoders can be implemented both in PCs and embedded systems. The DSPs (Digital Signal Processors) are platforms specialized in digital processing, being able to compute mathematical operations in a short period of time. Consequently, for this project the integration of the RVC-HEVC with calls to the OpenHEVC library will be done in a DSP platform such as a TMS320C6678. Once completed the integration, performance measures will be carried out to evaluate the improvement in the decoding speed obtained when optimized functions are used by the RVC-HEVC.

Um m��todo de otimiza����o da rela����o desempenho/consumo de energia para arquiteturas multi-cores heterog��neas em FPGA

Devido ��s tend��ncias de crescimento da quantidade de dados processados e a crescente necessidade por computa����o de alto desempenho, mudan��as significativas est��o acontecendo no projeto de arquiteturas de computadores. Com isso, tem-se migrado do paradigma sequencial para o paralelo, com centenas ou milhares de n��cleos de processamento em um mesmo chip. Dentro desse contexto, o gerenciamento de energia torna-se cada vez mais importante, principalmente em sistemas embarcados, que geralmente s��o alimentados por baterias. De acordo com a Lei de Moore, o desempenho de um processador dobra a cada 18 meses, por��m a capacidade das baterias dobra somente a cada 10 anos. Esta situa����o provoca uma enorme lacuna, que pode ser amenizada com a utiliza����o de arquiteturas multi-cores heterog��neas. Um desafio fundamental que permanece em aberto para estas arquiteturas �� realizar a integra����o entre desenvolvimento de c��digo embarcado, escalonamento e hardware para gerenciamento de energia. O objetivo geral deste trabalho de doutorado �� investigar t��cnicas para otimiza����o da rela����o desempenho/consumo de energia em arquiteturas multi-cores heterog��neas single-ISA implementadas em FPGA. Nesse sentido, buscou-se por solu����es que obtivessem o melhor desempenho poss��vel a um consumo de energia ��timo. Isto foi feito por meio da combina����o de minera����o de dados para a an��lise de softwares baseados em threads aliadas ��s t��cnicas tradicionais para gerenciamento de energia, como way-shutdown din��mico, e uma nova pol��tica de escalonamento heterogeneity-aware. Como principais contribui����es pode-se citar a combina����o de t��cnicas de gerenciamento de energia em diversos n��veis como o n��vel do hardware, do escalonamento e da compila����o; e uma pol��tica de escalonamento integrada com uma arquitetura multi-core heterog��nea em rela����o ao tamanho da mem��ria cache L1.

Partial Product Reduction based on Look-Up Tables

In this paper a new technique for partial product reduction based on the use of look-up tables for efficient processing is presented. We describe how to construct counter devices with pre-calculated data and their subsequent integration into the whole operation. The development of reduction trees organizations for this kind of devices uses the inherent integration benefits of computer memories and offers an alternative implementation to classic operation methods. Therefore, in our experiments we compare our implementation model with CMOS technology model in homogeneous terms.

An Electronic Reconfigurable Neural Architecture for Intrusion Detection

The explosive growth of the traffic in computer systems has made it clear that traditional control techniques are not adequate to provide the system users fast access to network resources and prevent unfair uses. In this paper, we present a reconfigurable digital hardware implementation of a specific neural model for intrusion detection. It uses a specific vector of characterization of the network packages (intrusion vector) which is starting from information obtained during the access intent. This vector will be treated by the system. Our approach is adaptative and to detecting these intrusions by using a complex artificial intelligence method known as multilayer perceptron. The implementation have been developed and tested into a reconfigurable hardware (FPGA) for embedded systems. Finally, the Intrusion detection system was tested in a real-world simulation to gauge its effectiveness and real-time response.

Agile Case Study Evaluation In Middle Size Project

In the last few years Agile methodologies appeared as a reaction to traditional ways of developing software and acknowledge the need for an alternative to documentation driven, heavyweight software development processes. This paper shortly presents a combination between Rational Uni ed Process and an agile approach for software development of e-business applications. The resulting approach is described stressing on the strong aspects of both combined methodologies. The article provides a case study of the proposed methodology which was developed and executed in a successful e-project in the area of the embedded systems.

Implementa����o de uma arquitetura fuzzy neural em hardware com treinamento online

Computational Intelligence Methods have been expanding to industrial applications motivated by their ability to solve problems in engineering. Therefore, the embedded systems follow the same idea of using computational intelligence tools embedded on machines. There are several works in the area of embedded systems and intelligent systems. However, there are a few papers that have joined both areas. The aim of this study was to implement an adaptive fuzzy neural hardware with online training embedded on Field Programmable Gate Array ��� FPGA. The system adaptation can occur during the execution of a given application, aiming online performance improvement. The proposed system architecture is modular, allowing different configurations of fuzzy neural network topologies with online training. The proposed system was applied to: mathematical function interpolation, pattern classification and selfcompensation of industrial sensors. The proposed system achieves satisfactory performance in both tasks. The experiments results shows the advantages and disadvantages of online training in hardware when performed in parallel and sequentially ways. The sequentially training method provides economy in FPGA area, however, increases the complexity of architecture actions. The parallel training method achieves high performance and reduced processing time, the pipeline technique is used to increase the proposed architecture performance. The study development was based on available tools for FPGA circuits.