Compiler-Directed Dynamic Voltage Scaling using Program Phases

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.

Coupling of High Voltage AC Power Line Fields to Metallic Pipelines

In the recent years, there has been a trend to run metallic pipelines carrying petroleum products and high voltage AC power lines parallel to each other in a relatively narrow strip of land. Due to this sharing of the right-of-way, verhead AC power line electric field may induce voltages on the metallic pipelines running in close vicinity leading to serious adverse effects. In this paper, the induced voltages on metallic pipelines running in close vicinity of high voltage power transmission lines have been computed. Before computing the induced voltages, an optimum configuration of the phase conductors based on the lowest conductor surface gradient and field under transmission line has been arrived at. This paper reports the conductor surface field gradients calculated for the various configurations. Also the electric fields under transmission line, for single circuit and double circuit (various phase arrangements) have been analyzed. Based on the above results, an optimum configuration giving the lowest field under the power line as well as the lowest conductor surface gradient has been arrived at and for this configuration, induced voltage on the pipeline has been computed using the Charge Simulation Method (CSM). For comparison, induced voltages on the pipeline has been computed for the various other phase configurations also.

Reactive interdiffusion: deviation from local equilibrium in the Fe-NiTiO3 couple

Deviation from local equilibrium between Fe–Ni alloy and (Fe,Ni)TiO3 solid solution in the reaction–diffusion zone of the Fe–NiTiO3 couple at 1273 K is evaluated by comparing the measured compositions in the zone with experimentally determined equilibrium tie-lines. The deviation is quantified by computing the Gibbs energy change for the reaction, Fe + NiTiO3 → FeTiO3 + Ni, from measured compositions in the zone and activity data available in the literature. Except near the extremities of the zone, the computed Gibbs energy change is constant, 8.2 kJ mol−1 higher than the standard Gibbs energy change for the reaction.

Effect of substrate bias voltage on the structure, electric and dielectric properties of TiO(2) thin films by DC magnetron sputtering

Titanium dioxide (TiO(2)) films have been deposited on glass and p-silicon (1 0 0) substrates by DC magnetron sputtering technique to investigate their structural, electrical and optical properties. The surface composition of the TiO(2) films has been analyzed by X-ray photoelectron spectroscopy. The TiO(2) films formed on unbiased substrates were amorphous. Application of negative bias voltage to the substrate transformed the amorphous TiO(2) into polycrystalline as confirmed by Raman spectroscopic studies. Thin film capacitors with configuration of Al/TiO(2)/p-Si have been fabricated. The leakage current density of unbiased films was 1 x10(-6) A/cm(2) at a gate bias voltage of 1.5 V and it was decreased to 1.41 x 10(-7) A/cm(2) with the increase of substrate bias voltage to -150 V owing to the increase in thickness of interfacial layer of SiO(2). Dielectric properties and AC electrical conductivity of the films were studied at various frequencies for unbiased and biased at -150 V. The capacitance at 1 MHz for unbiased films was 2.42 x 10(-10) F and it increased to 5.8 x 10(-10) F in the films formed at substrate bias voltage of -150 V. Dielectric constant of TiO(2) films were calculated from capacitance-voltage measurements at 1 MHz frequency. The dielectric constant of unbiased films was 6.2 while those formed at -150 V it increased to 19. The optical band gap of the films decreased from 3.50 to 3.42 eV with the increase of substrate bias voltage from 0 to -150 V. (C) 2011 Elsevier B. V. All rights reserved.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Alternating current conduction behavior of excimer laser ablated SrBi2Nb2O9 thin films

Bi-layered Aurivillius compounds prove to be efficient candidates of nonvolatile memories. SrBi2Nb2O9 thin films were deposited by excimer laser ablation at low substrate temperature (400 °C) followed by an ex situ annealing at 750 °C. The polarization hysteresis behavior was confirmed by variation of polarization with the external applied electric field and also verified with capacitance versus voltage characteristics. The measured values of spontaneous and remnant polarizations were, respectively, 9 and 6 μC/cm2 with a coercive field of 90 kV/cm. The measured dielectric constant and dissipation factors at 100 kHz were 220 and 0.02, respectively. The frequency analysis of dielectric and ac conduction properties showed a distribution of relaxation times due to the presence of multiple grain boundaries in the films. The values of activation energies from the dissipation factor and grain interior resistance were found to be 0.9 and 1.3 eV, respectively. The deviation in these values was attributed to the energetic conditions of the grain boundaries and bulk grains. The macroscopic relaxation phenomenon is controlled by the higher resistive component in a film, such as grain boundaries at lower temperatures, which was highlighted in the present article in close relation to interior grain relaxation and conduction properties.

Low‐voltage varistors based on zinc antimony spinel Zn7Sb2O12

It is possible to prepare low‐voltage varistors from the zinc antimony spinel Zn7Sb2O12 with breakdown voltages in the range of 3–20 V and nonlinearity coefficient α=7–15. The varistor property is due to the formation of high ohmic potential barriers at the grain boundary regions on low‐ohmic n‐type grain interiors of the polycrystalline samples. The method of preparation of the spinel, synthesized by coprecipitation followed by annealing under restricted partial pressures of oxygen, controls the mixed valence states for antimony, namely, Sb3+ and Sb5+. This is critical in attaining high nonlinearity and lower breakdown voltages.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

High voltage DC power supply topology for pulsed load applications with converter switching synchronized to load pulses

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. This paper proposes a methodology to tackle the problems associated with this type of application. Synchronization of converter switching with load pulses enables the converter to switch at half the load switching frequency. Low switching frequency helps in ensuring safety of HV transformer insulation and reduction of losses due to skin and proximity effect. Phase-modulated series resonant converter with ZVS is used as the power converter.

Input voltage modulated high voltage DC power supply topology for pulsed load applications

High voltage power supplies for radar applications are investigated which are subjected to pulsed load with stringent specifications. In the proposed solution, power conversion is done in two stages. A low power-high frequency converter modulates the input voltage of a high power-low frequency converter. This method satisfies all the performance specifications and takes care of the critical aspects of HV transformer.

Low threshold voltage ZnO thin film transistor with a Zn0.7Mg0.3O gate dielectric for transparent electronics

A highly transparent all ZnO thin film transistor (ZnO-TFT) with a transmittance of above 80% in the visible part of the spectrum, was fabricated by direct current magnetron sputtering, with a bottom gate configuration. The ZnO-TFT with undoped ZnO channel layers deposited on 300 nm Zn0.7Mg0.3O gate dielectric layers attains an on/off ratio of 104 and mobility of 20 cm2/V s. The capacitance-voltage (C−V) characteristics of the ZnO-TFT exhibited a transition from depletion to accumulation with a small hysteresis indicating the presence of oxide traps. The trap density was also computed from the Levinson’s plot. The use of Zn0.7Mg0.3O as a dielectric layer adds additional dimension to its applications. The room temperature processing of the device depicts the possibility of the use of flexible substrates such as polymer substrates. The results provide the realization of transparent electronics for next-generation optoelectronics.