Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Involvement of a cytosine side chain in proton transfer in the rate-determining step of ribozyme self-cleavage

Ribozymes of hepatitis delta virus have been proposed to use an active-site cytosine as an acid-base catalyst in the self-cleavage reaction. In this study, we have examined the role of cytosine in more detail with the antigenomic ribozyme. Evidence that proton transfer in the rate-determining step involved cytosine 76 (C76) was obtained from examining cleavage activity of the wild-type and imidazole buffer-rescued C76-deleted (C76Δ) ribozymes in D2O and H2O. In both reactions, a similar kinetic isotope effect and shift in the apparent pKa indicate that the buffer is functionally substituting for the side chain in proton transfer. Proton inventory of the wild-type reaction supported a mechanism of a single proton transfer at the transition state. This proton transfer step was further characterized by exogenous base rescue of a C76Δ mutant with cytosine and imidazole analogues. For the imidazole analogues that rescued activity, the apparent pKa of the rescue reaction, measured under kcat/KM conditions, correlated with the pKa of the base. From these data a Brønsted coefficient (β) of 0.51 was determined for the base-rescued reaction of C76Δ. This value is consistent with that expected for proton transfer in the transition state. Together, these data provide strong support for a mechanism where an RNA side chain participates directly in general acid or general base catalysis of the wild-type ribozyme to facilitate RNA cleavage.

Structural Analysis and Molecular Model of a Self-Incompatibility RNase from Wild Tomato1

Self-incompatibility RNases (S-RNases) are an allelic series of style glycoproteins associated with rejection of self-pollen in solanaceous plants. The nucleotide sequences of S-RNase alleles from several genera have been determined, but the structure of the gene products has only been described for those from Nicotiana alata. We report on the N-glycan structures and the disulfide bonding of the S3-RNase from wild tomato (Lycopersicon peruvianum) and use this and other information to construct a model of this molecule. The S3-RNase has a single N-glycosylation site (Asn-28) to which one of three N-glycans is attached. S3-RNase has seven Cys residues; six are involved in disulfide linkages (Cys-16-Cys-21, Cys-46-Cys-91, and Cys-166-Cys-177), and one has a free thiol group (Cys-150). The disulfide-bonding pattern is consistent with that observed in RNase Rh, a related RNase for which radiographic-crystallographic information is available. A molecular model of the S3-RNase shows that four of the most variable regions of the S-RNases are clustered on one surface of the molecule. This is discussed in the context of recent experiments that set out to determine the regions of the S-RNase important for recognition during the self-incompatibility response.

Reversible encapsulation by self-assembling resorcinarene subunits

Encapsulation complexes are assemblies in which a reversibly formed host more or less completely surrounds guest molecules. Host structures held together by hydrogen bonds have lifetimes in organic solvents of milliseconds to hours, long enough to directly observe the encapsulated guest by NMR spectroscopy. We describe here the action of alkyl ammonium compounds as guests that gather up to six molecules of the host module to form encapsulation complexes. The stoichiometry of the complexes—the largest hydrogen-bonded host capsules to date—is determined by the size and concentration of the guest.

Risk for engagement in nonsuicidal self-injury in children and adolescents

Although NSSI engagement is a growing public health concern, little research has documented the developmental precursors to NSSI in longitudinal studies using youth samples. This study aimed to expand upon previous research on groups of NSSI engagement in a population-based sample of youth using multi-wave data. Moreover, this study examined whether chronic peer and romantic stress, the serotonin transporter gene (5-HTTLPR), parenting behaviors, and negative attributional style predicted the NSSI group membership as well as the role of sex and grade. Participants were 549 youth in beginning in the 3rd, 6th, and 9th grades at the baseline assessment. NSSI was assessed across 7 waves of data. Chronic peer and romantic stress, 5-HTTLPR, parenting behaviors, and negative attributional style were assessed at baseline. Growth mixture models, conducted to test the latent trajectory of NSSI groups did not converge. Three NSSI groups were manually created according to classifications that were determined a priori. NSSI groups included: no NSSI (85.1%), episodic NSSI (8.5%), and repeated NSSI (6.4%). Chronic peer and romantic stress, sex, and grade differentiated the no NSSI vs. repeated NSSI groups and the episodic NSSI vs. repeated NSSI groups. Specifically, higher levels of stress, being female, and being in higher grades related to repeated NSSI. 5-HTTLPR differentiated the no NSSI vs. repeated NSSI groups, such that carrying the short allele of 5-HTTLPR related to repeated NSSI. Exploratory analyses revealed that the relationship between attributional style and NSSI group was moderated by grade. This study suggests chronic interpersonal peer and romantic stress is an important factor placing youth at greater risk for repeatedly engaging in NSSI.

Goal Orientation Profiles and Self-Concept of Secondary School Students

The objective of this study is to identify possible combinations of multiple goals that lead to different goal orientation profiles and to determine whether there are significant group differences in self-concept dimensions. The Achievement Goals Tendencies Questionnaire (AGTQ) and the Self-Description Questionnaire-II (SDQ-II) were administered to a sample of 2,022 students of Compulsory Secondary education, ranging in age from 12 to 16 years (M = 13.81, SD = 1.35). Cluster analysis identified four profiles of motivational goals: a group of students with a generalized high motivation profile, a group of students with generalized low motivation profile, a group of students with a predominance of learning goals and achievement goals, and a last group of students with a predominance of achievement goals and social reinforcement goals. Results reveal statistically significant differences among the profiles obtained regarding self-concept dimensions.

Motivational profiles Spanish students of Compulsory Secondary Education: Differential analysis of academic self-attributions

Academic goals and academic self-attributions are relevant variables in school settings. The objective of this study is to identify whether there are combinations of multiple goals that lead to different motivational profiles and to determine whether there are significant differences between the groups obtained regarding causal attributions of success and failure (ability, effort, or external causes) in Mathematics and Language and Literature, and in overall academic performance. The Goal Achievement Tendencies Questionnaire (AGTQ) and the Sydney Attribution Scale (SAS) were administered to a sample of 2022 students of compulsory secondary education, ranging in age from 12 to 16 years (M = 13.81, SD = 1.35). Cluster analysis identified four motivational profiles: a group of students with a high generalized motivation profile, a group of students with low generalized motivation profile, a group of students with predominance of learning goals and achievement goals, and a final group of students with predominance of social reinforcement goals. Results revealed statistically significant differences between the profiles obtained in academic self-attributions.

The perceived benefits of the chronic disease self-management program among participants with stroke: A qualitative study

Despite the expense associated with rehabilitation following stroke, dissatisfaction with psychosocial outcomes is common (Thomas & Parry, 1996). The rehabilitation system has been critiqued as lacking a theoretical base for psychosocial interventions (Goldberg, Segal, Berk, Schall, & Gershkoff, 1997). The current paper examines the possible role of the Chronic Disease Self-Management Program ([CDSMP] Lorig, 1996) in contributing to the psychosocial rehabilitation of people with stroke. This paper focuses on the analysis of incidental comments made by participants about a version of the CDSMP, tailored for people with stroke. These comments, collected over an 18-month follow-up period, provide interesting insights into the key aspects of the program. Six informative themes emerged from the more specific comments, namely (1) the importance of social contact and comparison, (2) increased awareness and knowledge about stroke, (3) motivation to pursue goals and activities, (4) a sense of achievement, (5) maintenance of gains, and (6) the paradoxical nature of social support. According to participants, the program was associated with enhanced self-efficacy. Other reported benefits (such as social support and enhanced knowledge) were indirectly associated with the program and appeared to reflect social aspects of the group and its stroke-specific focus. Maintenance of gains made by participants was seen as a crucial issue.

Self-determination theory: A case study of evidence-based coaching

The coach is central to the development of expertise in sport (Bloom, 1985) and is subsequently key to facilitating adaptive forms of motivation to enhance the quality of sport performance (Mallett & Hanrahan, 2004). In designing optimal training environments that are sensitive to the underlying motives of athletes, the coach requires an in-depth understanding of motivation. This paper reports on the application of self-determination theory (SDT; Deci & Ryan, 1985; Ryan & Deci, 2000) to coaching elite athletes. Specifically, the application of SDT to designing an autonomy-supportive motivational climate is outlined, which was used in preparing Australia's two men's relay teams for the 2004 Olympic Games in Athens.

Self-consistent theory of atomic Fermi gases with a Feshbach resonance at the superfluid transition

A self-consistent theory is derived to describe the BCS-Bose-Einstein-condensate crossover for a strongly interacting Fermi gas with a Feshbach resonance. In the theory the fluctuation of the dressed molecules, consisting of both preformed Cooper pairs and bare Feshbach molecules, has been included within a self-consistent T-matrix approximation, beyond the Nozieres and Schmitt-Rink strategy considered by Ohashi and Griffin. The resulting self-consistent equations are solved numerically to investigate the normal-state properties of the crossover at various resonance widths. It is found that the superfluid transition temperature T-c increases monotonically at all widths as the effective interaction between atoms becomes more attractive. Furthermore, a residue factor Z(m) of the molecule's Green function and a complex effective mass have been determined to characterize the fraction and lifetime of Feshbach molecules at T-c. Our many-body calculations of Z(m) agree qualitatively well with recent measurments of the gas of Li-6 atoms near the broad resonance at 834 G. The crossover from narrow to broad resonances has also been studied.

Uncertainty reduction, self-enhancement, and ingroup identification

Two experiments tested the prediction that uncertainty reduction and self-enhancement motivations have an interactive effect on ingroup identification. In Experiment 1 (N = 64), uncertainty and group status were manipulated, and the effect on ingroup identification was measured. As predicted, low-uncertainty participants identified more strongly with a high- than low-status group, whereas high-uncertainty participants showed no preference; and low-status group members identified more strongly under high than low uncertainty, whereas high-status group members showed no preference. Experiment 2 (N = 210) replicated Experiment 1, but with a third independent variable that manipulated how prototypical participants were of their group. As predicted, the effects obtained in Experiment 1 only emerged where participants were highly prototypical. Low prototypicality depressed identification with a low-status group under high uncertainty. The implications of these results for intergroup relations and the role of prototypicality in social identity processes are discussed.

A study of the lagged relationships among safety climate, safety motivation, safety behavior, and accidents at the individual and group levels

The authors measured perceptions of safety climate, motivation, and behavior at 2 time points and linked them to prior and subsequent levels of accidents over a 5-year period. A series of analyses examined the effects of top-down and bottom-up processes operating simultaneously over time. In terms of top-down effects, average levels of safety climate within groups at I point in time predicted subsequent changes in individual safety motivation. Individual safety motivation, in turn, was associated with subsequent changes in self-reported safety behavior. In terms of bottom-up effects, improvements in the average level of safety behavior within groups were associated with a subsequent reduction in accidents at the group level. The results contribute to an understanding of the factors influencing workplace safety and the levels and lags at which these effects operate.

Sharing Narratives Online: An international, self-organising curriculum in rural health

The aim of the Rural Medicine Rotation (RMR) at the University of Queensland (UQ) is to give all third year medical students exposure to and an understanding of, clinical practice in Australian rural or remote locations. A difficulty in achieving this is the relatively short period of student clinical placements, in only one or two rural or remote locations. A web-based Clinical Discussion Board (CDB) has been introduced to address this problem by allowing students at various rural sites to discuss their rural experiences and clinical issues with each other. The rationale is to encourage an understanding of the breadth and depth of rural medicine through peer-based learning. Students are required to submit a minimum of four contributions over the course of their six week rural placement. Analysis of student usage patterns shows that the majority of students exceeded the minimum submission criteria indicating motivation rather than compulsion to contribute to the CDB. There is clear evidence that contributing or responding to the CDB develops studentâ??s critical thinking skills by giving and receiving assistance from peers, challenging attitudes and beliefs and stimulating reflective thought. This is particularly evident in regard to issues involving ethics or clinical uncertainty, subject areas that are not in the medical undergraduate curriculum, yet are integral to real-world medical practice. The CDB has proved to be a successful way to understand the concerns and interests of third year medical students immersed in their RMR and also in demonstrating how technology can help address the challenge of supporting students across large geographical areas. We have recently broadened this approach by including students from the Rural Program at The Ohio State University College of Medicine. This important international exchange of ideas and approaches to learning is expected to broaden clinical training content and improve understanding of rural issues.

Do many hands make light work? How to overcome social loafing and gain motivation in work teams

Purpose – The purpose of this paper is to challenge the assumption that process losses of individuals working in teams are unavoidable. The paper aims to challenge this assumption on the basis of social identity theory and recent research. Design/methodology/approach – The approach adopted in this paper is to review the mainstream literature providing strong evidence for motivation problems of individuals working in groups. Based on more recent literature, innovative ways to overcome these problems are discussed. Findings – A social identity-based analysis and recent findings summarized in this paper show that social loafing can be overcome and that even motivation gains in group work can be expected when groups are important for the individual group members' self-concepts. Practical implications – The paper provides human resource professionals and front-line managers with suggestions as to how individual motivation and performance might be increased when working in teams. Originality/value – The paper contributes to the literature by challenging the existing approach to reducing social loafing, i.e. individualizing workers as much as possible, and proposes a team-based approach instead to overcome motivation problems.

Anger rumination and self-reported aggression amongst British and Hong Kong Chinese athletes: a cross cultural comparison

Previous work has determined relationships between provocation, anger rumination, and aggression in British athletes (Maxwell, 2004); however, the reliability of these findings and their generality across diverse cultures has not been examined. Therefore, a comparison of British and Hong Kong (HK) Chinese athletes’ propensity for rumination and aggression was undertaken. Provocation and thoughts of revenge were significantly associated with the self-reported aggression of both British and HK Chinese athletes. Frequency of aggression was similar across cultures except for a tendency for British male contact sport athletes to report greater frequency of aggressive behaviour. HK Chinese athletes tended to report higher frequencies of thoughts relating to understanding the causes of anger and higher incidence of perceived provocation. It was concluded that the pattern of aggressive behaviour was similar across the two cultures when opportunities for aggression are infrequent, but that HK Chinese athletes may inhibit aggressive responding even when opportunities are frequent.