459 resultados para Parallelism
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In this work, we study the types of paraphrases used by the students of the Language and Literature Course when they reformulate a source text in the theoretical section of the monographs produced as texts for the conclusion of the course. Our main goal is to know how the process of textual reformulation takes place in the production of the monographic gender. From the used theoretical orientation (Fuchs,1982; 1994; Charaudeau and Maingueneau, 2006; Fávero et al, 2007; Hilgert, 1997, 2002, 2006; among others) we have worked with the paraphrase notion as an activity of discoursive reformulation, considering as the basic groundings the situation of communication and the subjects, or the wider context. In a more specific way, we have considered that the paraphrase performs alterations in the formal level, in the semantic level and in the functional level. Besides that, we sought to articulate the practice of paraphrasing to the gender of discourse in which it appears and to the contextual implications involved in the producing of the gender in question, and in doing so we were grounded in Baktin´s (2003) and Maingueneau´s (1998; 2001) postulates. For the analysis of the corpus that consists of 19 monographs, we have used the three categories defined by Hilgert (2002, 2006):expansion, condensation and parallelism as a way of identifying, describing and characterizing the types of paraphrases used by the students who produced the monographs when they take up Travaglia´s (1996) text about the language conceptions. The results show that the use of the paraphrastic parallelism (with 69.45 % in relation to only 18.41% of condensation and 12.13 % of expansion) was the most recurrent in the reformulations performed by the students who produced the monographs and this manifestation was characterized mainly by the lexical-semantic repetition of fragments of the source text. We have concluded that the high incidence of paraphrastic parallelism is an indication that the student does not have a command of the ways of production and circulation of the discoursive genders uttered in the academic-scientific realm
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This work shows the design, simulation, and analysis of two optical interconnection networks for a Dataflow parallel computer architecture. To verify the optical interconnection network performance on the Dataflow architecture, we have analyzed the load balancing among the processors during the parallel programs executions. The load balancing is a very important parameter because it is directly associated to the dataflow parallelism degree. This article proves that optical interconnection networks designed with simple optical devices can provide efficiently the dataflow requirements of a high performance communication system.
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This work presents recent improvements in a density measurement cell with a double-element transducer that can eliminate diffraction effects. A new mechanical design combined with the use of more appropriate materials has resulted in better parallelism between interfaces, more robust assembly, and chemical resistance. A novel method of signal processing, named energy method, is introduced to obtain the reflection coefficient, reducing sensitivity to noise and improving accuracy. The measurement cell operation is verified both theoretically, using an acoustic wave propagation model, and experimentally, using homogeneous liquids with different densities. The accuracy in the density measurement is 0.2% when compared with the measurements made with a pycnometer.
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It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it
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The increase of applications complexity has demanded hardware even more flexible and able to achieve higher performance. Traditional hardware solutions have not been successful in providing these applications constraints. General purpose processors have inherent flexibility, since they perform several tasks, however, they can not reach high performance when compared to application-specific devices. Moreover, since application-specific devices perform only few tasks, they achieve high performance, although they have less flexibility. Reconfigurable architectures emerged as an alternative to traditional approaches and have become an area of rising interest over the last decades. The purpose of this new paradigm is to modify the device s behavior according to the application. Thus, it is possible to balance flexibility and performance and also to attend the applications constraints. This work presents the design and implementation of a coarse grained hybrid reconfigurable architecture to stream-based applications. The architecture, named RoSA, consists of a reconfigurable logic attached to a processor. Its goal is to exploit the instruction level parallelism from intensive data-flow applications to accelerate the application s execution on the reconfigurable logic. The instruction level parallelism extraction is done at compile time, thus, this work also presents an optimization phase to the RoSA architecture to be included in the GCC compiler. To design the architecture, this work also presents a methodology based on hardware reuse of datapaths, named RoSE. RoSE aims to visualize the reconfigurable units through reusability levels, which provides area saving and datapath simplification. The architecture presented was implemented in hardware description language (VHDL). It was validated through simulations and prototyping. To characterize performance analysis some benchmarks were used and they demonstrated a speedup of 11x on the execution of some applications
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The constant increase of complexity in computer applications demands the development of more powerful hardware support for them. With processor's operational frequency reaching its limit, the most viable solution is the use of parallelism. Based on parallelism techniques and the progressive growth in the capacity of transistors integration in a single chip is the concept of MPSoCs (Multi-Processor System-on-Chip). MPSoCs will eventually become a cheaper and faster alternative to supercomputers and clusters, and applications developed for these high performance systems will migrate to computers equipped with MP-SoCs containing dozens to hundreds of computation cores. In particular, applications in the area of oil and natural gas exploration are also characterized by the high processing capacity required and would benefit greatly from these high performance systems. This work intends to evaluate a traditional and complex application of the oil and gas industry known as reservoir simulation, developing a solution with integrated computational systems in a single chip, with hundreds of functional unities. For this, as the STORM (MPSoC Directory-Based Platform) platform already has a shared memory model, a new distributed memory model were developed. Also a message passing library has been developed folowing MPI standard
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This dissertation aims at extending the JCircus tool, a translator of formal specifications into code that receives a Circus specification as input, and translates the specification into Java code. Circus is a formal language whose syntax is based on Z s and CSP s syntax. JCircus generated code uses JCSP, which is a Java API that implements CSP primitives. As JCSP does not implement all CSP s primitives, the translation strategy from Circus to Java is not trivial. Some CSP primitives, like parallelism, external choice, communication and multi-synchronization are partially implemented. As an aditional scope, this dissertation will also develop a tool for testing JCSP programs, called JCSPUnit, which will also be included in JCircus new version. The extended version of JCircus will be called JCircus 2.0.
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The increasingly request for processing power during last years has pushed integrated circuit industry to look for ways of providing even more processing power with less heat dissipation, power consumption, and chip area. This goal has been achieved increasing the circuit clock, but since there are physical limits of this approach a new solution emerged as the multiprocessor system on chip (MPSoC). This approach demands new tools and basic software infrastructure to take advantage of the inherent parallelism of these architectures. The oil exploration industry has one of its firsts activities the project decision on exploring oil fields, those decisions are aided by reservoir simulations demanding high processing power, the MPSoC may offer greater performance if its parallelism can be well used. This work presents a proposal of a micro-kernel operating system and auxiliary libraries aimed to the STORM MPSoC platform analyzing its influence on the problem of reservoir simulation
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The increasing complexity of integrated circuits has boosted the development of communications architectures like Networks-on-Chip (NoCs), as an architecture; alternative for interconnection of Systems-on-Chip (SoC). Networks-on-Chip complain for component reuse, parallelism and scalability, enhancing reusability in projects of dedicated applications. In the literature, lots of proposals have been made, suggesting different configurations for networks-on-chip architectures. Among all networks-on-chip considered, the architecture of IPNoSys is a non conventional one, since it allows the execution of operations, while the communication process is performed. This study aims to evaluate the execution of data-flow based applications on IPNoSys, focusing on their adaptation against the design constraints. Data-flow based applications are characterized by the flowing of continuous stream of data, on which operations are executed. We expect that these type of applications can be improved when running on IPNoSys, because they have a programming model similar to the execution model of this network. By observing the behavior of these applications when running on IPNoSys, were performed changes in the execution model of the network IPNoSys, allowing the implementation of an instruction level parallelism. For these purposes, analysis of the implementations of dataflow applications were performed and compared
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Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors, requiring more efficient communication architectures, such as networks on chip (NoC). The NoCs are structures that have routers with channel point-to-point interconnect the cores of system on chip (SoC), providing communication. There are several networks on chip in the literature, each with its specific characteristics. Among these, for this work was chosen the Integrated Processing System NoC (IPNoSyS) as a network on chip with different characteristics compared to general NoCs, because their routing components also accumulate processing function, ie, units have functional able to execute instructions. With this new model, packets are processed and routed by the router architecture. This work aims at improving the performance of applications that have repetition, since these applications spend more time in their execution, which occurs through repeated execution of his instructions. Thus, this work proposes to optimize the runtime of these structures by employing a technique of instruction-level parallelism, in order to optimize the resources offered by the architecture. The applications are tested on a dedicated simulator and the results compared with the original version of the architecture, which in turn, implements only packet level parallelism
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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
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Cimetidine, referred as antiandrogenic agent, has caused alterations in the seminiferous tubules, including alterations in the peritubular tissue and death of myoid cells by apoptosis. Regarding the structural and functional importance of the peritubular tissue for the maintenance of Sertoli cells (SC), we purpose to investigate the SC-basement membrane interface, focusing the morphological features of SC and their interaction with the basement membrane in the affected tubules by cimetidine. Ten animals were distributed into two groups, control (CG) and cimetidine (CmG) which received saline solution and 50 mg of cimetidine per kg of body weight, respectively, for 52 days. The testes were fixed, dehydrated and embedded for analyses under light and transmission electron microscopy. Paraffin sections were submitted to the TUNEL method; sections of testes embedded in glycol methacrylate were submitted to PAS method and stained by H&E for morphological and quantitative analyses of Sertoli Cells. In the CmG, the SC nuclei were positive to the TUNEL method and showed typical morphological alterations of cell death by apoptosis (from early to advanced stages). A significant reduction in the number of Sertoli Cells was probably due to death of these cells by apoptosis. A close relationship between SC nuclear alterations (including a high frequency of dislocated nuclei from the basal portion) and damage in the peritubular tissue was observed. The ultrastructural analysis showed a parallelism between the gradual advancement of apoptotic process in SC and detachment of the anchoring sites (hemidesmosomes) of SC plasma membrane from the lamina densa. The presence of portions of lamina densa underlying the detached hemidesmosomes indicates a continuous deposition of lamina densa, resulting in the thickening of the basal lamina. The results indicate a possible disarrangement of the SC cytoskeleton, including the focal adhesion structure. These alterations are related to SC apoptosis and probably result from disturbs induced by cimetidine on the peritubular tissue.
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A new species of Aparasphenodon is described from patches of arboreal restinga within the Atlantic Forest Biome, in a region known as Baixo Sul in southern Bahia, northeastern Brazil. Aparasphenodon arapapa sp. nov. is promptly diagnosed from other Aparasphenodon mainly by having small size (male snout-vent length 57.4-58.1 mm), loreal region flattened and wide, and canthus rostralis rounded and poorly elevated. The wide and flattened snout resembles that found in Triprion and Diaglena, and possibly is a parallelism (homoplasy) related to the phragmotic behavior of casque-headed tree frogs to their microhabitat usage. The decision to allocate the new species in the genus Aparasphenodon is discussed in detail, as the single morphological synapomorphy of the genus, the presence of a prenasal bone, is insufficient to morphologically relate the new species to Aparasphenodon, Triprion, or Diaglena.
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The teleparallel gravity theory, treated physically as a gauge theory of translations, naturally represents a particular case of the most general gauge-theoretic model based on the general affine group of spacetime. on the other hand, geometrically, the Weitzenbock spacetime of distant parallelism is a particular case of the general metric-affine spacetime manifold. These physical and geometrical facts offer a new approach to teleparallelism. We present a systematic treatment of teleparallel gravity within the framework of the metric-affine theory. The symmetries, conservation laws and the field equations are consistently derived, and the physical consequences are discussed in detail. We demonstrate that the so-called teleparallel GR-equivalent model has a number of attractive features which distinguishes it among the general teleparallel theories, although it has a consistency problem when dealing with spinning matter sources.
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Neste artigo, discute-se a percepção de alguns estudiosos de que a pontuação demarca aspectos rítmicos da linguagem. Num primeiro momento, destaca-se a intuição dos estudiosos: (a) sobre aspectos métricos do ritmo (como simetria rítmica) e (b) tentativas de reprodução da linguagem (como os movimentos respiratórios, a alternância de características prosódicas da fala, a sensação de satisfação de expectativas e a de quebra de expectativas). Num segundo momento, destaca-se a intuição sobre aspectos do ritmo mais ligados a características da organização da linguagem em sua expressão escrita (como paralelismos rítmicos e unidades de idéias mais extensas)