High-speed conversion of xylose to l-lactate by electrodialysis bioprocess

Conversion of xylose to l-lactate was carried out by Lactococcus lactis IO-1 using an electrodialysis bioprocess (ED-BP). At 50 g l -1 xylose, the ED-BP was already complete in half the time (32 h) taken by the control culture without electrodialysis (>60 h). At 80 g l -1 xylose, the control culture was unable to consume >50 g l -1 xylose, whereas the ED-BP consumed 75 g l -1 xylose in 45 h. Thus, the simultaneous removal of lactate and acetate by ED-BP was associated with high-speed l-lactate production, increased xylose consumption and an increased l-lactate production. Copyright (C) 1998 Elsevier Science B.V.

Very high speed 17 Gbps SHACAL encryption architecture

Very high speed and low area hardware architectures of the SHACAL-1 encryption algorithm are presented in this paper. The SHACAL algorithm was a submission to the New European Schemes for Signatures, Integrity and Encryption (NESSIE) project and it is based on the SHA-1 hash algorithm. To date, there have been no performance metrics published on hardware implementations of this algorithm. A fully pipelined SHACAL-1 encryption architecture is described in this paper and when implemented on a Virtex-II X2V4000 FPGA device, it runs at a throughput of 17 Gbps. A fully pipelined decryption architecture achieves a speed of 13 Gbps when implemented on the same device. In addition, iterative architectures of the algorithm are presented. The SHACAL-1 decryption algorithm is derived and also presented in this paper, since it was not provided in the submission to NESSIE. © Springer-Verlag Berlin Heidelberg 2003.

Per-Flow State Management Technique for High-Speed Networks

Flow processing is a fundamental element of stateful traffic classification and it has been recognized as an essential factor for delivering today’s application-aware network operations and security services. The basic function within a flow processing engine is to search and maintain a flow table, create new flow entries if no entry matches and associate each entry with flow states and actions for future queries. Network state information on a per-flow basis must be managed in an efficient way to enable Ethernet frame transmissions at 40 Gbit/s (Gbps) and 100 Gbps in the near future. This paper presents a hardware solution of flow state management for implementing large-scale flow tables on popular computer memories using DDR3 SDRAMs. Working with a dedicated flow lookup table at over 90 million lookups per second, the proposed system is able to manage 512-bit state information at run time.

Broadband Green's Function and Applications to Fast Electromagnetic Analysis of High-Speed Interconnects

Thesis (Ph.D.)--University of Washington, 2015

Environmental and track perturbations on multiple pantograph interaction with catenaries in high-speed trains

The top velocity of high-speed trains is generally limited by the ability to supply the proper amount of energy through the pantograph-catenary interface. The deterioration of this interaction can lead to the loss of contact, which interrupts the energy supply and originates arcing between the pantograph and the catenary, or to excessive contact forces that promote wear between the contacting elements. Another important issue is assessing on how the front pantograph influences the dynamic performance of the rear one in trainsets with two pantographs. In this work, the track and environmental conditions influence on the pantograph-catenary is addressed, with particular emphasis in the multiple pantograph operations. These studies are performed for high speed trains running at 300 km/h with relation to the separation between pantographs. Such studies contribute to identify the service conditions and the external factors influencing the contact quality on the overhead system. (C) 2013 Elsevier Ltd. All rights reserved.

Cutting forces and wear analysis of Si3N4 diamond coated tools in high speed machining

Si3N4 tools were coated with a thin diamond film using a Hot-Filament Chemical Vapour Deposition (HFCVD) reactor, in order to machining a grey cast iron. Wear behaviour of these tools in high speed machining was the main subject of this work. Turning tests were performed with a combination of cutting speeds of 500, 700 and 900 m min−1, and feed rates of 0.1, 0.25 and 0.4 mm rot−1, remaining constant the depth of cut of 1 mm. In order to evaluate the tool behaviour during the turning tests, cutting forces were analyzed being verified a significant increase with feed rate. Diamond film removal occurred for the most severe set of cutting parameters. It was also observed the adhesion of iron and manganese from the workpiece to the tool. Tests were performed on a CNC lathe provided with a 3-axis dynamometer. Results were collected and registered by homemade software. Tool wear analysis was achieved by a Scanning Electron Microscope (SEM) provided with an X-ray Energy Dispersive Spectroscopy (EDS) system. Surface analysis was performed by a profilometer.

High-Speed Solid-Rotor Induction Machine – Electromagnetic Calculation and Design

Within the latest decade high-speed motor technology has been increasingly commonly applied within the range of medium and large power. More particularly, applications like such involved with gas movement and compression seem to be the most important area in which high-speed machines are used. In manufacturing the induction motor rotor core of one single piece of steel it is possible to achieve an extremely rigid rotor construction for the high-speed motor. In a mechanical sense, the solid rotor may be the best possible rotor construction. Unfortunately, the electromagnetic properties of a solid rotor are poorer than the properties of the traditional laminated rotor of an induction motor. This thesis analyses methods for improving the electromagnetic properties of a solid-rotor induction machine. The slip of the solid rotor is reduced notably if the solid rotor is axially slitted. The slitting patterns of the solid rotor are examined. It is shown how the slitting parameters affect the produced torque. Methods for decreasing the harmonic eddy currents on the surface of the rotor are also examined. The motivation for this is to improve the efficiency of the motor to reach the efficiency standard of a laminated rotor induction motor. To carry out these research tasks the finite element analysis is used. An analytical calculation of solid rotors based on the multi-layer transfer-matrix method is developed especially for the calculation of axially slitted solid rotors equipped with wellconducting end rings. The calculation results are verified by using the finite element analysis and laboratory measurements. The prototype motors of 250 – 300 kW and 140 Hz were tested to verify the results. Utilization factor data are given for several other prototypes the largest of which delivers 1000 kW at 12000 min-1.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

An efficient scheme for the evaluation of coding performance of high speed links incorporating joint error behaviour based on Monte Carlo Method

While channel coding is a standard method of improving a system’s energy efficiency in digital communications, its practice does not extend to high-speed links. Increasing demands in network speeds are placing a large burden on the energy efficiency of high-speed links and render the benefit of channel coding for these systems a timely subject. The low error rates of interest and the presence of residual intersymbol interference (ISI) caused by hardware constraints impede the analysis and simulation of coded high-speed links. Focusing on the residual ISI and combined noise as the dominant error mechanisms, this paper analyses error correlation through concepts of error region, channel signature, and correlation distance. This framework provides a deeper insight into joint error behaviours in high-speed links, extends the range of statistical simulation for coded high-speed links, and provides a case against the use of biased Monte Carlo methods in this setting

Simulation and Design of a high speed Solid State Switch for Excimer Laser

Excimerlaser sind gepulste Gaslaser, die Laseremission in Form von Linienstrahlung – abhängig von der Gasmischung – im UV erzeugen. Der erste entladungsgepumpte Excimerlaser wurde 1977 von Ischenko demonstriert. Alle kommerziell verfügbaren Excimerlaser sind entladungsgepumpte Systeme. Um eine Inversion der Besetzungsdichte zu erhalten, die notwendig ist, um den Laser zum Anschwingen zu bekommen, muss aufgrund der kurzen Wellenlänge sehr stark gepumpt werden. Diese Pumpleistung muss von einem Impulsleistungsmodul erzeugt werden. Als Schaltelement gebräuchlich sind Thyratrons, Niederdruckschaltröhren, deren Lebensdauer jedoch sehr limitiert ist. Deshalb haben sich seit Mitte der 1990iger Jahre Halbleiterschalter mit Pulskompressionsstufen auch in dieser Anwendung mehr und mehr durchgesetzt. In dieser Arbeit wird versucht, die Pulskompression durch einen direkt schaltenden Halbleiterstapel zu ersetzen und dadurch die Verluste zu reduzieren sowie den Aufwand für diese Pulskompression einzusparen. Zudem kann auch die maximal mögliche Repetitionsrate erhöht werden. Um die Belastung der Bauelemente zu berechnen, wurden für alle Komponenten möglichst einfache, aber leistungsfähige Modelle entwickelt. Da die normalerweise verfügbaren Daten der Bauelemente sich aber auf andere Applikationen beziehen, mussten für alle Bauteile grundlegende Messungen im Zeitbereich der späteren Applikation gemacht werden. Für die nichtlinearen Induktivitäten wurde ein einfaches Testverfahren entwickelt um die Verluste bei sehr hohen Magnetisierungsgeschwindigkeiten zu bestimmen. Diese Messungen sind die Grundlagen für das Modell, das im Wesentlichen eine stromabhängige Induktivität beschreibt. Dieses Modell wurde für den „magnetic assist“ benützt, der die Einschaltverluste in den Halbleitern reduziert. Die Impulskondensatoren wurden ebenfalls mit einem in der Arbeit entwickelten Verfahren nahe den späteren Einsatzparametern vermessen. Dabei zeigte sich, dass die sehr gebräuchlichen Class II Keramikkondensatoren für diese Anwendung nicht geeignet sind. In der Arbeit wurden deshalb Class I Hochspannungs- Vielschicht- Kondensatoren als Speicherbank verwendet, die ein deutlich besseres Verhalten zeigen. Die eingesetzten Halbleiterelemente wurden ebenfalls in einem Testverfahren nahe den späteren Einsatzparametern vermessen. Dabei zeigte sich, dass nur moderne Leistungs-MOSFET´s für diesen Einsatz geeignet sind. Bei den Dioden ergab sich, dass nur Siliziumkarbid (SiC) Schottky Dioden für die Applikation einsetzbar sind. Für die Anwendung sind prinzipiell verschiedene Topologien möglich. Bei näherer Betrachtung zeigt sich jedoch, dass nur die C-C Transfer Anordnung die gewünschten Ergebnisse liefern kann. Diese Topologie wurde realisiert. Sie besteht im Wesentlichen aus einer Speicherbank, die vom Netzteil aufgeladen wird. Aus dieser wird dann die Energie in den Laserkopf über den Schalter transferiert. Aufgrund der hohen Spannungen und Ströme müssen 24 Schaltelemente in Serie und je 4 parallel geschaltet werden. Die Ansteuerung der Schalter wird über hochisolierende „Gate“-Transformatoren erreicht. Es zeigte sich, dass eine sorgfältig ausgelegte dynamische und statische Spannungsteilung für einen sicheren Betrieb notwendig ist. In der Arbeit konnte ein Betrieb mit realer Laserkammer als Last bis 6 kHz realisiert werden, der nur durch die maximal mögliche Repetitionsrate der Laserkammer begrenzt war.

Development of directly modulated high speed telecommunication lasers based on surface defined feedback gratings

High-speed semiconductor lasers are an integral part in the implemen- tation of high-bit-rate optical communications systems. They are com- pact, rugged, reliable, long-lived, and relatively inexpensive sources of coherent light. Due to the very low attenuation window that exists in the silica based optical fiber at 1.55 μm and the zero dispersion point at 1.3 μm, they have become the mainstay of optical fiber com- munication systems. For the fabrication of lasers with gratings such as, distributed bragg reflector or distributed feedback lasers, etching is the most critical step. Etching defines the lateral dimmensions of the structure which determines the performance of optoelectronic devices. In this thesis studies and experiments were carried out about the exist- ing etching processes for InP and a novel dry etching process was de- veloped. The newly developed process was based on Cl2/CH4/H2/Ar chemistry and resulted in very smooth surfaces and vertical side walls. With this process the grating definition was significantly improved as compared to other technological developments in the respective field. A surface defined grating definition approach is used in this thesis work which does not require any re-growth steps and makes the whole fabrication process simpler and cost effective. Moreover, this grating fabrication process is fully compatible with nano-imprint lithography and can be used for high throughput low-cost manufacturing. With usual etching techniques reported before it is not possible to etch very deep because of aspect ratio dependent etching phenomenon where with increasing etch depth the etch rate slows down resulting in non-vertical side walls and footing effects. Although with our de- veloped process quite vertical side walls were achieved but footing was still a problem. To overcome the challenges related to grating defini- tion and deep etching, a completely new three step gas chopping dry etching process was developed. This was the very first time that a time multiplexed etching process for an InP based material system was demonstrated. The developed gas chopping process showed extra ordinary results including high mask selectivity of 15, moderate etch- ing rate, very vertical side walls and a record high aspect ratio of 41. Both the developed etching processes are completely compatible with nano imprint lithography and can be used for low-cost high-throughput fabrication. A large number of broad area laser, ridge waveguide laser, distributed feedback laser, distributed bragg reflector laser and coupled cavity in- jection grating lasers were fabricated using the developed one step etch- ing process. Very extensive characterization was done to optimize all the important design and fabrication parameters. The devices devel- oped have shown excellent performance with a very high side mode suppression ratio of more than 52 dB, an output power of 17 mW per facet, high efficiency of 0.15 W/A, stable operation over temperature and injected currents and a threshold current as low as 30 mA for almost 1 mm long device. A record high modulation bandwidth of 15 GHz with electron-photon resonance and open eye diagrams for 10 Gbps data transmission were also shown.

1.55 µm High-Speed QDs Lasers for Optical Telecommunication Applications

In this work investigation of the QDs formation and the fabrication of QD based semiconductor lasers for telecom applications are presented. InAs QDs grown on AlGaInAs lattice matched to InP substrates are used to fabricate lasers operating at 1.55 µm, which is the central wavelength for far distance data transmission. This wavelength is used due to its minimum attenuation in standard glass fibers. The incorporation of QDs in this material system is more complicated in comparison to InAs QDs in the GaAs system. Due to smaller lattice mismatch the formation of circular QDs, elongated QDs and quantum wires is possible. The influence of the different growth conditions, such as the growth temperature, beam equivalent pressure, amount of deposited material on the formation of the QDs is investigated. It was already demonstrated that the formation process of QDs can be changed by the arsenic species. The formation of more round shaped QDs was observed during the growth of QDs with As2, while for As4 dash-like QDs. In this work only As2 was used for the QD growth. Different growth parameters were investigated to optimize the optical properties, like photoluminescence linewidth, and to implement those QD ensembles into laser structures as active medium. By the implementation of those QDs into laser structures a full width at half maximum (FWHM) of 30 meV was achieved. Another part of the research includes the investigation of the influence of the layer design of lasers on its lasing properties. QD lasers were demonstrated with a modal gain of more than 10 cm-1 per QD layer. Another achievement is the large signal modulation with a maximum data rate of 15 Gbit/s. The implementation of optimized QDs in the laser structure allows to increase the modal gain up to 12 cm-1 per QD layer. A reduction of the waveguide layer thickness leads to a shorter transport time of the carriers into the active region and as a result a data rate up to 22 Gbit/s was achieved, which is so far the highest digital modulation rate obtained with any 1.55 µm QD laser. The implementation of etch stop layers into the laser structure provide the possibility to fabricate feedback gratings with well defined geometries for the realization of DFB lasers. These DFB lasers were fabricated by using a combination of dry and wet etching. Single mode operation at 1.55 µm with a high side mode suppression ratio of 50 dB was achieved.