Avian diversification patterns across the K-Pg boundary: Influence of calibrations, datasets, and model misspecification

Birds represent the most diverse extant tetrapod clade, with ca. 10,000 extant species, and the timing of the crown avian radiation remains hotly debated. The fossil record supports a primarily Cenozoic radiation of crown birds, whereas molecular divergence dating analyses generally imply that this radiation was well underway during the Cretaceous. Furthermore, substantial differences have been noted between published divergence estimates. These have been variously attributed to clock model, calibration regime, and gene type. One underappreciated phenomenon is that disparity between fossil ages and molecular dates tends to be proportionally greater for shallower nodes in the avian Tree of Life. Here, we explore potential drivers of disparity in avian divergence dates through a set of analyses applying various calibration strategies and coding methods to a mitochondrial genome dataset and an 18-gene nuclear dataset, both sampled across 72 taxa. Our analyses support the occurrence of two deep divergences (i.e., the Palaeognathae/Neognathae split and the Galloanserae/Neoaves split) well within the Cretaceous, followed by a rapid radiation of Neoaves near the K-Pg boundary. However, 95% highest posterior density intervals for most basal divergences in Neoaves cross the boundary, and we emphasize that, barring unreasonably strict prior distributions, distinguishing between a rapid Early Paleocene radiation and a Late Cretaceous radiation may be beyond the resolving power of currently favored divergence dating methods. In contrast to recent observations for placental mammals, constraining all divergences within Neoaves to occur in the Cenozoic does not result in unreasonably high inferred substitution rates. Comparisons of nuclear DNA (nDNA) versus mitochondrial DNA (mtDNA) datasets and NT- versus RY-coded mitochondrial data reveal patterns of disparity that are consistent with substitution model misspecifications that result in tree compression/tree extension artifacts, which may explain some discordance between previous divergence estimates based on different sequence types. Comparisons of fully calibrated and nominally calibrated trees support a correlation between body mass and apparent dating error. Overall, our results are consistent with (but do not require) a Paleogene radiation for most major clades of crown birds.

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router

A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. The router design is optimized to avoid FIFO buffers at the input port and loop back at output crossbar. It provides virtual channels to emulate a non-blocking network and supports a simple X-Y relative addressing scheme to limit the control overhead to 9 bits per packet. The 8times8 honeycomb NoC (RECONNECT) implemented in 130 nm UMC CMOS standard cell library operates at 500 MHz and has a bisection bandwidth of 28.5 GBps. The network is characterized for random, self-similar and application specific traffic patterns that model the execution of multimedia and DSP kernels with varying network loads and virtual channels. Our implementation with 4 virtual channels has an average network latency of 24 clock cycles and throughput of 62.5% of the network capacity for random traffic. For application specific traffic the latency is 6 clock cycles and throughput is 87% of the network capacity.

Yrittäjyyden arvottaminen akateemisten nuorten argumentoinnissa

Evaluation of entrepreneurship in the speech of academic students and newly qualified young academics a summary of a qualitative attitude study. In Finland very few university students plan to become entrepreneurs. The aim of this research was to examine entrepreneurial attitudes expressed in speech. The material was gathered from interviews with university students and newly qualified young academic adults. The interviewees commented on twelve different sentences with claims formulated using research literature and views that have appeared in public discussions. The interviewees were divided into three different groups based on their self-expressed entrepreneurial intentions. The method of qualitative attitude research (Vesala & Rantanen 1999, 2007) was used in the interviews. The research material was studied using two interpretative theories: (1) The planned behaviour theory (Ajzen 1985, 1991a, b), which makes it possible to focus on the separate elements (attitude towards an act, subjective norms and perceived feasibility) necessary for intentions to develop; and (2) The theory of the two images of entrepreneurship (Vesala 1996), where individualism and relationism can be seen as resources for evaluating entrepreneurship. The subject of the research was how university students and newly qualified young adults viewed entrepreneurship as a general phenomen and in relation to the academic world. A second focus was on the attitudes expressed toward entrepreneurial university education and the possibility of combining entrepreneurship and academic knowledge. Of interest were also questions such as whether academic studies, knowledge and the university itself are resources or barriers to entrepreneurial intentions and entrepreneurship whether university students received any support for their entrepreneurial ambitions from the university and their fellow academic students. The problems tackled by this research were thus the following: How was entrepreneurship seen, both as a general phenomen and in an academic context, when it was evaluated positively, negatively or neutrally by the interviewees? In what way was entrepreneurship constructed in the interviewees attitudes? How were entrepreneurship and the academic world related in the interviewees attitudes? What kind of role did the university as an academic context play in the interviewees attitudes for example were university education and academic knowledge seen as resources or barriers to their entrepreneurial intentions. Traditional attitude studies claim that attitudes are a stable property of an individual. In contrast, rhetorical social psychological and qualitative attitude studies emphasize the contextual and linguistic aspects of attitude, and they offered an alternative viewpoint for this research. The study was based on two general assumptions: attitudes have objects and are evaluative. Here attitude was defined as an evaluative interpresentation made towards an object; adopting an attitude is a contextual process in the sense that attitudes are always concerned with the action context of the persons presenting them. Entrepreneurship, both as a general phenomen and in an academic context, was specified as the object to which an attitude was taken. From a theoretical point of view, qualitative methods suited the general structure of this research well. In a particular, qualitative approach which emphasized contextual elements proved to be both empirically valid and useful for avoiding the problematic assumptions associated with traditional attitude study. The subject of the analysis was the argumentative speech produced by the interviewees. The results of the study show the subjects responses to three main ways of viewing entrepreneurships. The first was an individualistic, ideal image of entrepreneurship. This was mostly evaluated positively and gained wide approval especially among interviewees who included entrepreneurship among their employment choices. Entrepreneurship was seen as the decision to earn one s living independently. In this individualistic image of entrepreneurship, the social context was hardly ever mentioned. Elements which were seen to threaten this ideal image were evaluated negatively. When entrepreneurship was evaluated negatively using the individualistic image of entrepreneurship, it was mentioned that it forced one into a never ending cycle of work and uninterested duties. The relationistic image of entrepreneurship was used as a speech resource when the social context was constructed as an economic resource or a threat to the ideal image of entrepreneurship. In the second view, entrepreneurship was characteristically seen as being based on economics, which was seen as a threat to the ideal individualistic image of entrepreneurship. The risk of economic failure was seen as a limiting factor to entrepreneurial ambitions as it forced entrepreneurs to work around the clock. The third view concerned the relationship between entrepreneurship and the academic world. Entrepreneurship as an employment choice for university educated persons was evaluated as relevant, and thus positively, when university education was constructed as a resource for entrepreneurship - and irrelevant and thus negatively when it was construed as an obstacle, too wide, or when successful entrepreneurship was seen as being mostly based on an individual s personal characteristics. The interviewees with no entrepreneurial intentions expressed the view that academic education didn t provide the proper skills and knowledge for entrepreneurship. The interviewees also expressed interest in university entrepreneurship education, although none had experience on this. The interviewees emphasized the fact that the University didn t encourage them to consider entrepreneurship as a relevant employment choice. The assumption made by this study was that becoming an entrepreneur is a conscious decision, the environment may influence an individual s decisions on how to make a living as it tends to socialise people to act in accordance with cultural traditions. Keywords: Entrepreneurship, Attitudes towards entrepreneurship, Intentional behaviour, Entrepreneurial intention, University entrepreneurship education, Qualitative attitude research (Vesala & Rantanen 1999, 2007), Rhetorical social psychology (Billig 1986), The theory of entrepreneuship s two images: individualism and relationism (Vesala 1996 ), The planned behaviour theory (Ajzen 1985, 1991a, b)

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Exploring energy-performance trade-offs for heterogeneous interconnect clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires which leads to delay in execution and significantly high energy consumption.In this paper, we propose a new instruction scheduling algorithm that exploits scheduling slacks of instructions and communication slacks of data values together to achieve better energy-performance trade-offs for clustered architectures with heterogeneous interconnect. Our instruction scheduling algorithm achieves 35% and 40% reduction in communication energy, whereas the overall energy-delay product improves by 4.5% and 6.5% respectively for 2 cluster and 4 cluster machines with marginal increase (1.6% and 1.1%) in execution time. Our test bed uses the Trimaran compiler infrastructure.

Domestic labour relations in India : Vulnerability and gendered life courses in Jaipur

This study explores labour relations between domestic workers and employers in India. It is based on interviews with both employers and workers, and ethnographically oriented field work in Jaipur, carried out in 2004-2007. Combining development studies with gender studies, labour studies, and childhood studies, it asks how labour relations between domestic workers and employers are formed in Jaipur, and how female domestic workers trajectories are created. Focusing on female part-time maids and live-in work arrangements, the study analyses children s work in the context of overall work force, not in isolation from it. Drawing on feminist Marxism, domestic labour relations are seen as an arena of struggle. The study takes an empirical approach, showing class through empiria and shows how paid domestic work is structured and stratified through intersecting hierarchies of class, caste, gender, age, ethnicity and religion. The importance of class in domestic labour relations is reiterated, but that of caste, so often downplayed by employers, is also emphasized. Domestic workers are crucial to the functioning of middle and upper middle class households, but their function is not just utilitarian. Through them working women and housewives are able to maintain purity and reproduce class disctinctions, both between poor and middle classes and lower and upper middle classes. Despite commodification of work relations, traditional elements of service relationships have been retained, particularly through maternalist practices such as gift giving, creating a peculiar blend of traditional and market practices. Whilst employers of part-time workers purchase services in a segmented market from a range of workers for specific, traditional live-in workers are also hired to serve employers round the clock. Employers and workers grudgingly acknowledged their dependence on one another, employers seeking various strategies to manage fear of servant crime, such as the hiring of children or not employing live-in workers in dual-earning households. Paid domestic work carries a heavy stigma and provide no entry to other jobs. It is transmitted from mothers to daughters and working girls were often the main income providers in their families. The diversity of working conditions is analysed through a continuum of vulnerability, generic live-in workers, particularly children and unmarried young women with no close family in Jaipur, being the most vulnerable and experienced part-time workers the least vulnerable. Whilst terms of employment are negotiated informally and individually, some informal standards regarding salary and days off existed for maids. However, employers maintain that workings conditions are a matter of individual, moral choice. Their reluctance to view their role as that of employers and the workers as their employees is one of the main stumbling blocks in the way of improved working conditions. Key words: paid domestic work, India, children s work, class, caste, gender, life course

Role of population transfer under strong probe conditions in electromagnetically induced transparency

We analyze theoretically the phenomenon of electromagnetically induced transparency (UT) under conditions where the probe laser is not in the usual weak limit. We consider the effects in both three-level and four-level systems, which are either closed or open (due to losses to an external metastable level). We find that the EIT dip almost disappears in a closed three-level system but survives in an open system. In four-level systems, there is a narrow enhanced-absorption peak (EITA) at line center, which has applications as an optical clock. The peak converts to an EIT dip in a closed system, but again survives in an open system. (C) 2010 Elsevier B.V. All rights reserved.

Accelerating multi-core simulators

Simulation is an important means of evaluating new microarchitectures. With the invention of multi-core (CMP) platforms, simulators are becoming larger and more complex. However, with the availability of CMPs with larger caches and higher operating frequency, the wall clock time required for simulating an application has become comparatively shorter. Reducing this simulation time further is a great challenge, especially in the case of multi-threaded workload due to indeterminacy introduced due to simultaneously executing various threads. In this paper, we propose a technique for speeding multi-core simulation. The model of the processor core and cache are replaced with functional models, to achieve speedup. A timed Petri net model is used to estimate the execution time of the processor and the memory access latencies are estimated using hit/miss information obtained from the functional model of the cache. This model can be used to predict performance of data parallel applications or multiprogramming workload on CMP platform with various cache hierarchies and shared bus interconnect. The error in estimation of the execution time of an application is within 6%. The speedup achieved ranges between an average of 2x--4x over the cycle accurate simulator.

Conflict-Tolerant Real-Time Specifications in Metric Temporal Logic

A framework based on the notion of "conflict-tolerance" was proposed in as a compositional methodology for developing and reasoning about systems that comprise multiple independent controllers. A central notion in this framework is that of a "conflict-tolerant" specification for a controller. In this work we propose a way of defining conflict-tolerant real-time specifications in Metric Interval Temporal Logic (MITL). We call our logic CT-MITL for Conflict-Tolerant MITL. We then give a clock optimal "delay-then-extend" construction for building a timed transition system for monitoring past-MITL formulas. We show how this monitoring transition system can be used to solve the associated verification and synthesis problems for CT-MITL.

Capturing higher modes of vibration of micromachined resonators

MEMS resonators have potential applications in the areas of RF-MEMS, clock oscillators, ultrasound transducers, etc. The important characteristics of a resonator are its resonant frequency and Q-factor (a measure of damping). Usually large damping in macro structures makes it difficult to excite and measure their higher modes. In contrast, MEMS resonators seem amenable to excitation in higher modes. In this paper, 28 modes of vibration of an electrothermal actuator are experimentally captured–perhaps the highest number of modes experimentally captured so far. We verify these modes with FEM simulations and report that all the measured frequencies are within 5% of theoretically predicted values.

Design and Implementation of a Flexible and Memory Efficient Operating System for Sensor Nodes

Sensor network nodes exhibit characteristics of both embedded systems and general-purpose systems.A sensor network operating system is a kind of embedded operating system, but unlike a typical embedded operating system, sensor network operatin g system may not be real time, and is constrained by memory and energy constraints. Most sensor network operating systems are based on event-driven approach. Event-driven approach is efficient in terms of time and space.Also this approach does not require a separate stack for each execution context. But using this model, it is difficult to implement long running tasks, like cryptographic operations. A thread based computation requires a separate stack for each execution context, and is less efficient in terms of time and space. In this paper, we propose a thread based execution model that uses only a fixed number of stacks. In this execution model, the number of stacks at each priority level are fixed. It minimizes the stack requirement for multi-threading environment and at the same time provides ease of programming. We give an implementation of this model in Contiki OS by separating thread implementation from protothread implementation completely. We have tested our OS by implementing a clock synchronization protocol using it.

Believe it or Not! Multicore CPUs can Match GPUs for FLOP-intensive Applications

In this work, we evaluate performance of a real-world image processing application that uses a cross-correlation algorithm to compare a given image with a reference one. The algorithm processes individual images represented as 2-dimensional matrices of single-precision floating-point values using O(n4) operations involving dot-products and additions. We implement this algorithm on a nVidia GTX 285 GPU using CUDA, and also parallelize it for the Intel Xeon (Nehalem) and IBM Power7 processors, using both manual and automatic techniques. Pthreads and OpenMP with SSE and VSX vector intrinsics are used for the manually parallelized version, while a state-of-the-art optimization framework based on the polyhedral model is used for automatic compiler parallelization and optimization. The performance of this algorithm on the nVidia GPU suffers from: (1) a smaller shared memory, (2) unaligned device memory access patterns, (3) expensive atomic operations, and (4) weaker single-thread performance. On commodity multi-core processors, the application dataset is small enough to fit in caches, and when parallelized using a combination of task and short-vector data parallelism (via SSE/VSX) or through fully automatic optimization from the compiler, the application matches or beats the performance of the GPU version. The primary reasons for better multi-core performance include larger and faster caches, higher clock frequency, higher on-chip memory bandwidth, and better compiler optimization and support for parallelization. The best performing versions on the Power7, Nehalem, and GTX 285 run in 1.02s, 1.82s, and 1.75s, respectively. These results conclusively demonstrate that, under certain conditions, it is possible for a FLOP-intensive structured application running on a multi-core processor to match or even beat the performance of an equivalent GPU version.

Energy Reduction in SRAM using Dynamic Voltage and Frequency Management

This paper describes a dynamic voltage frequency control scheme for a 256 X 64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100 MHz to I GHz. The supply voltage of the complete memory system is varied in steps of 50 mV over the range of 500 mV to IV. The threshold voltage range of operation is plusmn100 mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy-performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy-delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure. (C) 2012 Elsevier Inc. All rights reserved.