Design and implementation of the embedded capacitance layers for decoupling of wireless sensor nodes

In this paper, the embedded capacitance material (ECM) is fabricated between the power and ground layers of the wireless sensor nodes, forming an integrated capacitance to replace the large amount of decoupling capacitors on the board. The ECM material, whose dielectric constant is 16, has the same size of the wireless sensor nodes of 3cm*3cm, with a thickness of only 14μm. Though the capacitance of a single ECM layer being only around 8nF, there are two reasons the ECM layers can still replace the high frequency decoupling capacitors (100nF in our case) on the board. The first reason is: the parasitic inductance of the ECM layer is much lower than the surface mount capacitors'. A smaller capacitance value of the ECM layer could achieve the same resonant frequency of the surface mount decoupling capacitors. Simulation and measurement fit this assumption well. The second reason is: more than one layer of ECM material are utilized during the design step to get a parallel connection of the several ECM capacitance layers, finally leading to a larger value of the capacitance and smaller value of parasitic. Characterization of the ECM is carried out by the LCR meter. To evaluate the behaviors of the ECM layer, time and frequency domain measurements are performed on the power-bus decoupling of the wireless sensor nodes. Comparison with the measurements of bare PCB board and decoupling capacitors solution are provided to show the improvement of the ECM layer. Measurements show that the implementation of the ECM layer can not only save the space of the surface mount decoupling capacitors, but also provide better power-bus decoupling to the nodes.

GENESI: Wireless sensor networks for structural monitoring

The GENESI project has the ambitious goal of bringing WSN technology to the level where it can provide the core of the next generation of systems for structural health monitoring that are long lasting, pervasive and totally distributed and autonomous. This goal requires embracing engineering and scientific challenges never successfully tackled before. Sensor nodes will be redesigned to overcome their current limitations, especially concerning energy storage and provisioning (we need devices with virtually infinite lifetime) and resilience to faults and interferences (for reliability and robustness). New software and protocols will be defined to fully take advantage of the new hardware, providing new paradigms for cross-layer interaction at all layers of the protocol stack and satisfying the requirements of a new concept of Quality of Service (QoS) that is application-driven, truly reflecting the end user perspective and expectations. The GENESI project will develop long lasting sensor nodes by combining cutting edge technologies for energy generation from the environment (energy harvesting) and green energy supply (small form factor fuel cells); GENESI will define models for energy harvesting, energy conservation in super-capacitors and supplemental energy availability through fuel cells, in addition to the design of new algorithms and protocols for dynamic allocation of sensing and communication tasks to the sensors. The project team will design communication protocols for large scale heterogeneous wireless sensor/actuator networks with energy-harvesting capabilities and define distributed mechanisms for context assessment and situation awareness. This paper presents an analysis of the GENESI system requirements in order to achieve the ambitious goals of the project. Extending from the requirements presented, the emergent system specification is discussed with respect to the selection and integration of relevant system components.The resulting integrated system will be evaluated and characterised to ensure that it is capable of satisfying the functional requirements of the project

Energy storage systems for wave energy converters and microgrids

The thesis initially gives an overview of the wave industry and the current state of some of the leading technologies as well as the energy storage systems that are inherently part of the power take-off mechanism. The benefits of electrical energy storage systems for wave energy converters are then outlined as well as the key parameters required from them. The options for storage systems are investigated and the reasons for examining supercapacitors and lithium-ion batteries in more detail are shown. The thesis then focusses on a particular type of offshore wave energy converter in its analysis, the backward bent duct buoy employing a Wells turbine. Variable speed strategies from the research literature which make use of the energy stored in the turbine inertia are examined for this system, and based on this analysis an appropriate scheme is selected. A supercapacitor power smoothing approach is presented in conjunction with the variable speed strategy. As long component lifetime is a requirement for offshore wave energy converters, a computer-controlled test rig has been built to validate supercapacitor lifetimes to manufacturer’s specifications. The test rig is also utilised to determine the effect of temperature on supercapacitors, and determine application lifetime. Cycle testing is carried out on individual supercapacitors at room temperature, and also at rated temperature utilising a thermal chamber and equipment programmed through the general purpose interface bus by Matlab. Application testing is carried out using time-compressed scaled-power profiles from the model to allow a comparison of lifetime degradation. Further applications of supercapacitors in offshore wave energy converters are then explored. These include start-up of the non-self-starting Wells turbine, and low-voltage ride-through examined to the limits specified in the Irish grid code for wind turbines. These applications are investigated with a more complete model of the system that includes a detailed back-to-back converter coupling a permanent magnet synchronous generator to the grid. Supercapacitors have been utilised in combination with battery systems for many applications to aid with peak power requirements and have been shown to improve the performance of these energy storage systems. The design, implementation, and construction of coupling a 5 kW h lithium-ion battery to a microgrid are described. The high voltage battery employed a continuous power rating of 10 kW and was designed for the future EV market with a controller area network interface. This build gives a general insight to some of the engineering, planning, safety, and cost requirements of implementing a high power energy storage system near or on an offshore device for interface to a microgrid or grid.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

Computational modeling of defects in nanoscale device materials

This PhD thesis concerns the computational modeling of the electronic and atomic structure of point defects in technologically relevant materials. Identifying the atomistic origin of defects observed in the electrical characteristics of electronic devices has been a long-term goal of first-principles methods. First principles simulations are performed in this thesis, consisting of density functional theory (DFT) supplemented with many body perturbation theory (MBPT) methods, of native defects in bulk and slab models of In0.53Ga0.47As. The latter consist of (100) - oriented surfaces passivated with A12O3. Our results indicate that the experimentally extracted midgap interface state density (Dit) peaks are not the result of defects directly at the semiconductor/oxide interface, but originate from defects in a more bulk-like chemical environment. This conclusion is reached by considering the energy of charge transition levels for defects at the interface as a function of distance from the oxide. Our work provides insight into the types of defects responsible for the observed departure from ideal electrical behaviour in III-V metal-oxidesemiconductor (MOS) capacitors. In addition, the formation energetics and electron scattering properties of point defects in carbon nanotubes (CNTs) are studied using DFT in conjunction with Green’s function based techniques. The latter are applied to evaluate the low-temperature, low-bias Landauer conductance spectrum from which mesoscopic transport properties such as the elastic mean free path and localization length of technologically relevant CNT sizes can be estimated from computationally tractable CNT models. Our calculations show that at CNT diameters pertinent to interconnect applications, the 555777 divacancy defect results in increased scattering and hence higher electrical resistance for electron transport near the Fermi level.

Magnetophoretic circuits for digital control of single particles and cells.

The ability to manipulate small fluid droplets, colloidal particles and single cells with the precision and parallelization of modern-day computer hardware has profound applications for biochemical detection, gene sequencing, chemical synthesis and highly parallel analysis of single cells. Drawing inspiration from general circuit theory and magnetic bubble technology, here we demonstrate a class of integrated circuits for executing sequential and parallel, timed operations on an ensemble of single particles and cells. The integrated circuits are constructed from lithographically defined, overlaid patterns of magnetic film and current lines. The magnetic patterns passively control particles similar to electrical conductors, diodes and capacitors. The current lines actively switch particles between different tracks similar to gated electrical transistors. When combined into arrays and driven by a rotating magnetic field clock, these integrated circuits have general multiplexing properties and enable the precise control of magnetizable objects.

WAVES IN 2D ANISOTROPIC L-C LATTICE METAMATERIALS:PHENOMENOLOGY AND PROPERTIES

Anisotropic metamaterials composed of 2D periodic infi- nite and finite periodic lattices of lumped inductor (L) and capacitor (C) circuits have been explored. The unique features of wave channeling on such anisotropic lattices and scattering at their interfaces and edges are reviewed and illustrated by the examples of the specific arrangements. The lattice unit cells composed of inductors and capacitors (basic mesh) as well as of assemblies comprised of double series, double parallel, and mixed parallel-series L-C circuits are discussed.

Low temperature surface nitridation processes for dielectric-Ge interfaces

Germanium MOS capacitors have been fabricated with a high-? HfO dielectric using ALD. An in-situ low temperature (250°C) nitrogen plasma treatment on the germanium surface prior to the deposition of HfO was found to be beneficial to the electrical properties of the devices. Germanium MOS capacitors have also been fabricated with a SiO dielectric deposited by an atmospheric pressure CVD 'silox' process. The same low temperature plasma nitridation was found to degrade the electrical properties of the silox devices. The effect of a post-metal anneal in H and N on both types of capacitor structure was also found to degrade device electrical properties. copyright The Electrochemical Society.

Evidence for two-phase regions in BST thin films from capacitance-voltage data

The Curie-Weiss plots of reciprocal dielectric constant versus temperature, in Ba0.5Sr0.5TiO3 films grown onto SrRuO3 lower electrodes by pulsed-laser deposition, show two minima below film thicknesses of 280 nm. This double minima implies possible mixed phases in the thin films. A graphical plot of capacitance for decreasing dc voltage versus that of increasing dc voltage shows a well-defined triangular shape for both Pb(Zr0.4Ti0.6)O-3 and SrBi2Ta2O9 thin films. However, for a 175-nm-thick Ba0.5Sr0.5TiO3 thin film, the plot shows an overlapping of two triangles, suggesting mixed phases. This graphical method appears to be effective in detecting structural subtleties in ferroelectric capacitors.

Electrode field penetration: A new interpretation of tunneling currents in barium strontium titanate (BST) thin films

This paper shows that penetration of the applied electric field into the electrodes of a ferroelectric thin film capacitor produces both an interfacial capacitance and an effective mechanism for electron tunneling. The model predictions are compared with experimental results on Au-BST-SrRuO3 capacitors of varying thicknesses, and the agreement is excellent.

Ancients inspire modern memory

A stencilling technique for depositing arrays of nanoscale ferroelectric capacitors on a surface could be useful in data storage devices.

Thin film capacitor cut from single crystals using focused ion beam milling

The focused ion beam microscope (FIB) has been used to fabricate thin parallel-sided ferroelectric capacitors from single crystals of BaTiO3 and SrTiO3. A series of nano-sized capacitors ranging in thickness from similar to660 nm to similar to300 nm were made. Cross-sectional high resolution transmission electron microscopy (HRTEM) revealed that during capacitor fabrication, the FIB rendered around 20 nm of dielectric at the electrode-dielectric interface amorphous, associated with local gallium impregnation. Such a region would act electrically in series with the single crystal and would presumably have a considerable negative influence on the dielectric properties. However, thermal annealing prior to gold electrodes deposition was found to fully recover the single crystal capacitors and homogenise the gallium profile. The dielectric testing of the STO ultra-thin single crystal capacitors was performed yielding a room temperature dielectric constant of similar to300, as is the case in bulk. Therefore, there was no evidence of a collapse in dielectric constant associated with thin film dimensions.

Atomic layer deposition of hafnium oxide dielectrics on silicon and germanium substrates

Hafnium oxide films have been deposited at 250 °C on silicon and germanium substrates by atomic layer deposition (ALD), using tetrakis-ethylmethylamino hafnium (TEMAH) and water vapour as precursors in a modified Oxford Instruments PECVD system. Self-limiting monolayer growth has been verified, characterised by a growth rate of 0.082 nm/ cycle. Layer uniformity is approximately within ±1% of the mean value. MOS capacitors have been fabricated by evaporating aluminium electrodes. CV analysis has been used to determine the bulk and interface properties of the HfO 2, and their dependence on pre-clean schedule, deposition conditions and post-deposition annealing. The dielectric constant of the HfO 2 is typically 18. On silicon, best results are obtained when the HfO 2 is deposited on a chemically oxidised hydrophilic surface. On germanium, best results are obtained when the substrate is nitrided before HfO 2 deposition, using an in-situ nitrogen plasma treatment. © Springer Science+Business Media, LLC 2007.

Ferroelectrics at the Nanoscale

There are several factors which make the investigation and understanding of nanoscale ferroelectrics particularly timely and important. Firstly, there is a market pressure, primarily from the electronics industry, to integrate ferroelectrics into devices with progressive decreases in size and increases in morphological complexity. This is perhaps best illustrated through the roadmaps for product development in FeRAM (Ferroelectric Randorn Access Memory) where the need for increases in bit density will require a move from 2D planar capacitor structures to 3D trenched capacitors in the next few years. Secondly, there is opportunity for novel exploration, as it is only relatively recently that developments in thin film growth of complex oxides, self-assembly techniques and high-resolution 'top-down' patterning have converged to allow the fabrication of isolated and well-defined ferroelectric nanoshapes, the properties of which are not known. Thirdly, there is an expectation that the behaviour of small scale ferroelectrics will be different from bulk, as this group of functional materials is highly sensitive to boundary/surface conditions, which are expected to dominate the overall response when sizes are reduced into the nanoscale regime. This feature article attempts to introduce some of the current areas of discovery and debate surrounding studies on ferroelectrics at the nanoscale. The focus is directed primarily at the search for novel size-related properties and behaviour which are not necessarily observed in bulk.

THEORY AND DESIGN OF A TUNABLE QUASI-LUMPED QUADRATURE COUPLER

In this article, we present the theory and a design methodology for a unable Quasi-Lumped Quadrature Coupler (QLQC). Because of its topology, the coupler is simply reconfigured by switching the bias of two varactor diodes via a very simple DC bias circuitry. No additional capacitors or inductors are required. A prototype at 3.5 GHz is etched on a 0.130-mm-thick layer substrate with a dielectric material of relative permittivity of 2.22. The simulated and measured scattering parameters are, presented. (c) 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2219-2222 2009: Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24526